Research On TSV Test And Diagnosis Method For 3D Integrated Circuits

With the shrinking of transistor feature sizes,the development of integrated circuits meets bottlenecks.To meet the new requirements of integrated circuits development,the Through-silicon Via(TSV)based Three-dimensional Integrated Circuit(3D IC)technology was proposed as a promising solution.By stacking a number of dies vertically using TSV,3D IC gains higher integration,smaller area overhead,lower delay and lower power consumption.Since TSV is a new type interconnection whose technology is not yet mature,various of defects may occur in TSV manufacturing or 3D IC bonding process.In Wafer Probe process,TSV test and fault diagnosis can not only guarantee the effectiveness and reliability of TSV,leading a better yield,but also decrease the final cost of products.Therefore,the research on TSV test and fault diagnosis in Wafer Probe process has both academic value and practical significance.This dissertation mainly focuses on test and diagnosis issues of TSV in digital 3D IC.The main contributions of this dissertation are described as follow:(1)For the lack of parametric TSV defect models,a TSV defect modeling method based on Finite Element Analysis is proposed.By modeling and analysing common TSV defects(void,open,leakage,misalignment.etc)using Q3 D and HFSS software,TSV RLGC equivalent circuits of defect models have been built,which shows the functional relationship between the physical parameters of TSV defects and electrical parameters of RLGC equivalent circuit models.Compared with other existing TSV defects modeling methods,the proposed defect models are more accuracy and more comprehensive.(2)To decrease the high cost in pre-bond TSV probing,a pre-bond TSV probing test method based on IEEE 1149.1 is proposed.By reusing test resources,judging faults in-line,and implementing test process in digital,the proposed IEEE 1149.1 based DfT structure can effectively decrease the test cost.(3)For the low test accuracy and weak robustness problems in pre-bond TSV test,a pre-bond TSV on-chip test method based on Switched-capacitor is proposed.Firstly,by insteading of the capacitor in Switched-capacitor circuits using TSV,the capacitance of TSV can be presented by a adjustable equivalent resistor R.Secondly,by connecting R with a known capacitor of C,we built a RC discharging circuit through which TSV capacitance C can be calculated.Thirdly,we judge the TSV faulty or not by comparing the calculated C.The overall test circuits are implemented by a design-for-testibility structure on chip.Compared with other existing pre-bond TSV test methods,the proposed method can capture test responses more easily since equivalent resistor R is adjustable.Besides,using special DfT design,the test results would not be affected by the process variation,signal skew and signal jitter,thus leading a higher test resolution and a better robustness.(4)To improve the test accuracy and fault diagnosis capability in post-bond stage,a TSV test and diagnosis method based on RGC parameters measurement is proposed.In this method,the capacitance of TSV is precisely measured through Switched-capacitor circuit.By eliminating the error caused by ON-resistance of TG using calibration method,TSV resistance and conductance are measured through RC charging/discharging circuit.Based on the TSV defect models and the measured RGC parameters,the proposed method can test and diagnose TSV faults.The overall test circuits are implemented by a designfor-testibility structure on chip.Compared with other existing post-bond TSV test methods,the proposed method can not only detect faulty TSV more effectively,but also diagnose the causes and degrees of faults based on the TSV defect models and the measured RGC parameters.