Research On RTL Fault Models And Test Generation

Integrated circuit (IC) testing plays an important role on guaranteeingreliability of circuit. The growing complexity of Ics is bringing a big problemto circuit testing. Test Generation is an important part of testing. Theory andmethod of testing are firstly summarized. Some methods of RTL testing andmodel analysis are also presented in this dissertation.Main contributions are listed as follows.1. An approach is presented to cover inside branches of states. To coverinside branches of a state, state transfer tokens were inserted into the code.Original transfer between two states is extended to several ones. So, testpatterns generated based on the modified code can cover inside branches of astate. A formal deception is presented to explain this approach. Thisdissertation also proposes an algorithm to generate test pattern. Traversal ofdirected state graph could help to collect patterns that can test sequentialcircuit. Experiment conducted on ITC99 benchmark reveals that this methodis more effective. It achieves the same coverage as VTG in average.Furthermore, the length of generated test sequence is reduced by 50%.2. Merit and shortcoming of traditional states covering method and geneticmethod are analyzed. A new genetic selecting approach is presented toovercome the shortcoming of these two methods. First, it can be implementedat RT-Level. Second, it uses state coverage as fitness function, which is usefulto test the control-part of circuit. Third, it can test control part and data part ofa circuit at the same time. Concepts about DST (Dynamic State Transfer) andSST (Static State Transfer) are also brought up in this dissertation to directTPG(Test Pattern Generation). Based on this approach, an ATPG tool namedGRTT is developed. Experimental results for ITC99 benchmarks demonstratethat the proposed method can speed up X-Pulling by more than 1 order ofmagnitude.3. There are no effective fault models defined at high level. To solve thisproblem, two kinds of relationships between different fault models areanalyzed. Relationship between a high-level fault model and stuck-at faultmodel (defined at gate level) is analyzed, followed by analysis of relationshipbetween two high level fault models. These relationships are expected tofound one or a set of effective high-level fault models. High-level faultmodels founded are expected to direct ATPG(automatic test pattern generation)and DFT(Design For Test) more effectively than traditional ones. Experimentconducted on benchmark of itc99 demonstrates this approach. Three kind ofhigh-level fault models are analyzed, transfer fault model, states fault modeland branch fault model.