Research On TSVs Fault-Tolerance In3D ICs

Improvement of the Integrated Circuits(ICs) complexity and development ofthe semiconductor manufacturing technology make more and more devices couldbe integrated on a single chip, which is a challenge to upgrade the performance ofthe ICs because of the power rapidly get increased and the wiring get morecomplicated. Researchers proposed Three-Dimensional Integrated Circuits(3DICs)for further increase the integratation and the performance. Adopting3D-Stacked-Die implementation could improve the performance, reduce the areaand the signal delay, which is considered to have broad prospects.However, the research on3D ICs is still at the beginning stage and itsdevelopment faces with many challenges. Numerous Through-Silicon-Vias(TSVs)are used as the vertical interconnect wires, but at the manufacturing stage the TSVswould be failure because of the limitation of the semiconductor manufacturingtechnology. As a way of repairing the fault, fault-tolerant techniques could increasethe reliability of the system, so configurable fault-tolerant schemes are used toresume the failure TSVs in3D ICs.This thesis proposed a configurable fault-tolerant scheme based onmulti-chains to resume the failed TSV. In this scheme, many TSVs are divided intoa TSV chain and four TSV chains are divided into a TSV block, then two redundantTSVs are added in each TSV block. If a failure occurs in TSVs, the architecturewill be reconstructed and the redundant TSV replaces the failure TSV to transmitsignals. Comparing with existing TSV fault-tolerant architecture this scheme notonly can decrease the number of redundant TSV, but also decrease the complexityand increase the resume ratio.But there are already numerous TSVs in3D ICs, adopting the configurablefault-tolerance scheme based on multi-chains, the area cost is expensive if add twoadditional redundant TSVs in each block. Muxes and buffers are added on thecritical path, which also increase the signal delay. We proposed a configurablefault-tolerance scheme based on crossbar switch unit to further reduce the numberof redundant TSVs. The TSVs will be interconnected to the crossbar switch unitafter they are divided into multi TSV chains. If a failure occurs in a TSV, the circuitwill be reconstructed to tolerate the fault. According to the experiments, not only can our scheme increase the resume ration, but also can reduce the number of theredundant TSVs and the delay.