The Research On Fault Tolerance Of TSV For Three Dimension Integrated Circuit

Now, as the technology of three demension integrated circuit is an arising research hotspot, It has drawn more and more attentions from industries and academics. Multiple chips have been stacked vertically by Through-Silicon-Via (TSV), which brings many advantages, such as low power consumption, high bandwidth, small size, good performance, supporting of heterogeneous integration, etc. The technology of three dimensional integrated circuits is an important method for the continuation of Moore’s law. Comparing with the tranditional integrated circuits, three-dimensional integrated circuits have the obvious advantage in performance, however, TSV manufacturing process is not yet mature. Leakage fault and resistive open fault of TSVs seriously affect the yield and reliability of 3D integrated circuit. Yield problem has become the main factors that affect the commercialization of 3D integrated circuits. The main research contents of the paper are as fellows:1. Study the basic knowledge and the advantages of the three-dimensional integrated circuit, and explore the influence of the TSV defects on the yield of three-dimensional integrated circuit. To figure out the failure mechanism of TSV, The TSV fault types which caused by TSV defects are analyzed, then the parameters of TSV are modeled by HSPICE.2. Learn the existing TSV fault tolerance method, according to their fault tolerance mechanism of TSV, they can be divided into two types:the test fault tolerance and the on-line fault tolerance. Based on the existing theoretical study of the TSV tolerance scheme, This paper focuse on the advantages and disadvantages of these two kinds of fault-tolerant programs and a new TSV online tolerance scheme is explored.3. Aiming at the deficiency of 3D ICs’ yield and the disadvantages of previous methods, this paper proposes a double TSV self-online tolerance scheme. This scheme can reduce the failure probability of TSV by using the mutual coupling channel structure, and it can be used to repair the leakage of TSV and the open circuit fault automatically. Experimental results show that our scheme can perform online tolerance for the leakage fault and resistive open fault without any consumption of test time and pins of the circuit, and efficiently improve the reliability and yield of 3D ICs while the normal operation of the circuit is not affected.