NBTI Aging Analysis And Aging-tolerant Design Of Level Shifter

Negative Bias Temperature Instability(NBTI)-induced PMOS transistor aging has become a prominent reliability concern in the nano-scaled IC design.NBTI directly effect PMOS,the electrical properties of PMOS have been degenerate such as the threshold voltage rise and the increasing delay,eventually result to the circuit malfunction.Multi voltage design is an effective way to reduce power in modern IC,level shifter circuit is inserted between different voltage domains for meeting the signal transfer between different voltage domains.Performance of a multi voltage circuit can be affected,if NBTI effect level shifter.In this paper,the NBTI aging analysis is carried out for the two traditional level shifter structures,and the improved design is made to allow its ability to tolerate aging.In this thesis,the cross coupled level shifter(CCLS)was studied.Influences of NBTI aging effect on the performance of CCLS are analyzed though HSPICE,and the improved design has been presented.These are cross coupled PMOS and NMOS in CCLS.The strong contention between the pull-up and pull-down network,if pull-up and pull-down are mismatching.NBTI can affect the pull-up of PMOS,aggravates the competition.The improved design has been proposed in this thesis.The Diode-PMOS has been insert between pull-up PMOS and pull-down NMOS for restrain competition.And multi threshold technology has been used to reduce the delay of the circuit.The experimental results show that,compared with the original level shifter circuit,the new circuit can word under lower input low voltage,the power consumption and time delay of different input voltages are greatly reduced,it has great ability to tolerate aging.The current mirror level shifter(CMLS)was also studied in this thesis.Influences of NBTI aging effect on the performance of CCLS are analyzed,and the improved design has been presented.CCLS has large power,and NBTI result in the increasing delay.Because There will be a direct leakage circuit of the power voltage to the ground in the circuit,so CC The leakage current is restricted by inserting a transmission gate in the key leakage current path in the CMLS circuit and multi threshold technology has been used to reduce the delay,the improved design has been proposed.The experimental results show that,compared with the original level shifter circuit,the new circuit can word under lower input low voltage,the power consumption and time delay of different input voltages are greatly reduced,it has low power and great ability to tolerate aging.