Research On Prediction And Tolerance On Integrated-circuits Aging

With the advances in manufacturing technology, supply voltage continuously reduces andintegration density keeps on rising, achieving a high development of integrated circuit industry.Along with integrated circuit technology developing, aging of integrated circuit becomes more andmore serious. Negative bias temperature instability (NBTI), emerging as one of the major agingmechanisms, attracts lots of attention.This dissertation focuses on NBTI-induced aging prediction and dynamic circuit aging-tolerantdesign.(1) For aging failure prediction of integrated circuit, we optimized an existing aging sensor,which can detect multi-fault and eliminate the error induced by structure factor.(2) Foraging-tolerant of integrated circuit design, many domino logic circuits, as a key role ofhigh-performance integrated circuits, are studied. This thesis proposed an aging-tolerant Dominologic circuit design and a low-leakage and NBTI-mitigated domino logic technique.The main contributions are as follows:(1) A low-cost multi-fault detector. Though multi-fault detection is one of the hot topics in faultdetection region, previous work can not achieve a good compromise among function, chip area andpower. Classical aging sensors adapt a stability checker constructed by a dynamic circuit with agreat many of feedback devices, resulting in expensive area overhead, and conspicuous powerconsumption. A pulse generator is proposed, as the alternative of the stability checker, which greatlyreduced area overhead and power overhead.(2) An improved on-line aging-predict scheme. In contrast to the unbalance detection capabilityof existing aging sensors, an improved prediction aging sensor scheme is proposed, which utilizesthe symmetrical NOR gate to balance the detection capability, eliminating the detection error causedby the stacking effect in the stability checker.(3) Targeting NBTI-induced aging in domino logic circuits, a scheme is presented to maintainthe performance through compensation circuit. Domino logic circuits are extensively applied intime-critical path(s) in high performance microprocessors. For the degrading delay and unity noisegain due to NBTI-induced aging in domino logic circuits, a domino logic circuit with compensationcircuit is presented, whose compensation circuit works after domino logic circuit aged. Theproposed scheme not only prolongs the circuit lifetime but also avoid high power consumption. Thislow-power and aging-tolerant circuit technology is promising.(4) A circuit technique to mitigate NBTI-induced degradation and reduce standby leakagecurrent in standby mode. Existing technologies for reducing leakage of domino logic circuitsexacerbates NBTI-induced aging. The proposed technique controls input vector and internal node toforce both keeper and inverter PMOS transistor transforming into aging-recovery mode in standbymode, resulting in the decrement of leakage current of domino circuit. Experimental resultsdemonstrates that, as a multi-objective optimization solution, the proposed technique achieves up to33%NBTI-induced degradation reduction and up to79%leakage current reduction.