NBTI Aging Analysis And Aging-tolerant Design Of 32nm CMOS Domino Cell Circuits

Negative Bias Temperature Instability (NBTI)-induced PMOS transistor aging has become a prominent reliability concern in the nano-scaled IC design. NBTI will cause a shift in the threshold voltages, increasing the delay of PMOS devices, potentially leading to a functional failure. As an important branch of dynamic circuit, domino circuits is also affected by the NBTI effect and lead to a serious performance degradation. In tradition, increasing the size of the transistor at the design stage adds ample timing margin of the circuit to ensure circuit performance during the entire life, but leading high area/power overheads. This method is not suitable for large-scale digital integrated circuit design is obvious. Therefore, this dissertation focuses on NBTI aging analysis and aging-tolerant design of domino unit circuits.In this paper, the impact of NBTI on the performances of 32nm P-type domino AND gates which are used widely for designing high performance digital integrated circuits, is analyzed by HSPICE simulation. Experimental results show that, the time delay of the 32nm technology P-type domino AND gate affected by NBTI aging for a decade, increases up to 11.450%. Considering the difference of the impact of different part of PMOS transistors NBTI aging on AND gate performance, a new P-type domino AND gate is proposed with multi-threshold voltage PMOS transistors configuration scheme introduced. A relatively low threshold voltage is assigned to the transistor Pclk to provide the circuit with sufficient timing margin to deal with NBTI-induced time delay degradation under NBTI, and the threshold voltage of transistors in the pull-up network is increased a little to compensate the noise-tolerant ability reduction and power increase. Compared with the existing P-type domino AND gate, the proposed AND gate can provide 0.828% timing margin after circuit aging with same noise margin and 0.916% power consumption reduced, so that the lifetime of domino circuit is guaranteed.Unlike the P-type domino circuit noise margin increases due to the threshold voltage shift of the pull-up network, the aging of the keeper degrades the noise-tolerant ability of the N-type domino circuit. The traditional dual-threshold voltage design will degrades the noise-tolerant ability by lowering the threshold voltage of the transistor on the critical path. The NBTI aging analysis of 32nm N-type domino OR unit circuit by HSPICE simulation show that keeper and inverter PMOS keep same threshold voltage can ensure constant noise immunity. Based on the above conclusions, a new dual-threshold voltage N-type domino OR gate is proposed, a relatively low threshold voltage is assigned to the inverter PMOS to provide the circuit with sufficient timing margin, and the threshold voltage of keeper keeps same with inverter PMOS to compensate the noise-tolerant ability reduction. Compared with the existing N-type domino OR gate, the proposed OR gate can provide 0.358% timing margin after circuit aging with same noise margin, indicating the effectiveness of the proposed dual-threshold voltage of the N-type domino OR gate.