| Power management chip is an indispensable part and directly affects the power consumption and the standby time of each mobile terminal. The defect interaction between design and manufacturing process can cause current leakage failure that has become the main factor restricting the product yield of power management chip.Before chip could be batched released into market, it must be batch manufacturing within accepted yield range. But from the integrated circuit design to batch manufacturing, exist a step of yield enhancement, which cost certain time. The real time of product to market should conclude the design and verification time. So the rapid yield enhancement has become the urgent need for the integrated circuit design house opening market and earning profit.This paper selected a kind of mobile terminal’s power management chip, to perform current leakage failure analysis, which is being used currently. For the data analysis aspect, sampling 100 wafers, use cumulative stack distribution method to analyze CP data of current leakage to generate distribution map. For electrical analysis aspect, use 4156C (Precision Semiconductor Parameter Analyzer) to measure I-V curve, use the Emission microscopy and OBIRCH to catch the defect location. Then use AFM (Atomic Force Microscopy) and NanoProbe to perform failure mode analysis. For the physical analysis aspect, use the physical delayer method, FIB (Focused Ion Beam), SEM (Scanning Electron Microscope), chemical composition analysis of defects and VC (Voltage Contrast) positioning methodology to establish the failure mode. Through researching, found the failure root cause, coordinated with production line engineer to study the failure mode, then found the yield enhancement method. |
