Research On Low Trigger ESD Protection Device And ESD Soft Failure Measurement Method

When the first chip was born,Electrostatic Discharge(ESD)seriously threatened the safety of integrated circuit products.Therefore,in the integrated circuit industry,ESD has caused extremely serious losses.On the one hand,the upper limit voltage and lower limit voltage of ESD protection design window are gradually close.Therefore,in the design of low-voltage ESD protection,the hysteresis ESD protection device requires a lower voltage when the device is triggered.On the other hand,as portable mobile electronic products gradually enter human daily life,the soft failure of system level ESD also seriously affects the use feeling of these electronic products.ESD protection in this thesis involves two stages of integrated circuit products.On the one hand,SCR(Silicon Controlled Rectifier)has the best robustness per unit area.However,its too large trigger voltage and too small maintenance voltage make it unable to be directly used in the actual ESD protection design.In the low-voltage ESD protection design,the maintenance voltage of SCR is no longer a problem.On this basis,this thesis presents a novel low trigger voltage ESD protection device.On the other hand,the analysis method of system level ESD soft failure is accompanied by experiment and simulation.Due to the extremely complex systems of devices such as portable mobile electronic products,this results in a huge workload for the analysis process.This thesis conducts related research based on the above two aspects,and the research contents are as follows:(1)This thesis presents a low trigger voltage ESD protection device,namely MLVTSCR(modified low voltage triggered SCR).The structure uses the rising edge of the ESD pulse to assist its parasitic SCR current path to open to reduce the trigger voltage.The experimental results show that the minimum trigger voltage of MLVTSCR can reach2.86 V.By comparing the simulated HBM voltage waveforms of MLVTSCR and LVTSCR,the first peak of mlvtscr is reduced by 30.2% and the second peak is reduced by 8.6%.However,the second peak of MLVTSCR is still very high,so this thesis proposes another new low trigger voltage ESD protection device,namely LVDTSCR(low voltage diode triggered SCR).The device replaces the PMOS transistor in the MLVTSCR with a reverse diode,which greatly reduces its second peak by 78% without changing the mlvtscr trigger mechanism.(2)This thesis presents a baseline test method for ESD soft failure.The method divides soft failures into immediate and accidental types according to their frequency.For the accidental type that is difficult to find,it is necessary to introduce high-voltage pulse generator to assist TLP test.Experiments show that the number of soft failures does not increase with voltage in the occasional case.And the frequency of the pulse increases,and the number of soft failures generally increases.On this basis,the test method can not only obtain the soft failure baseline,but also reduce the workload of the experiment.