10G Ethernet UDP/IP Processor Video Based On FPGA Design Of Transmission Interface

At present,the rapid development of network vehicle safety technology requires not only to monitor the real-time vehicle condition ahead,but also to monitor the surrounding road conditions.So,many cameras are used to monitor different azimuth states at the same time.The TCP/IP network communication protocol is realized by traditional software,which can not meet the fast processing function when receiving a large amount of data,and the built-in protocol of ASIC is not convenient to transplant the shortcomings of the poor flexibility activity.1000 M network can not deal with multiple cameras to receive data in real time.The processing speed of internal processing can be greatly improved by using FPGA pure hardware.At the same time,the internal transmission of data in parallel can be easier to implement 10 Gbps width.The system is mainly divided into three modules: video image acquisition and storage module design,UDP/IP protocol stack design,10 G Ethernet MAC controller design.The function module of video image acquisition and storage function,the initialization of the camera and the configuration of the camera parameters,and the data read or write to the SDRAM chip by the SDRAM controller.The UDP/IP protocol stack module uses full duplex mode,encapsulates the collected video data into Ethernet frames,and then assembles the 8bit bit width into the 64 bit bit width to the 10 G MAC controller.For data reception,the 64 bit data received from the 10 G MAC controller is sent to the protocol stack in sequence according to the 8bit data,and the data is parsed and the video data is obtained.The design of UDP/IP protocol stack is composed of sending module,receiving module and MAC interface module.he 10 GMAC controller is designed according to the IEEE802.3ea specification.The flow control principle,the 64 bit parallel CRC check code,the number of inserted frame intervals and the XGMII interface are analyzed and studied.The whole controller is designed with 64 bit bit width for data transmission.The working clock is in 156.25 MHz.The internal composition is divided into the transmission module,the receiving module,the flow control module and the XGMII interface module.The main devices used include Altera's FPGA chip,Cyclone IV EP4CE10F17C8 C,camera sensor OV7670,Winbond's SDRAM chip and VGA interface.In the system implementation,the Verilog language is used to describe the function.In the QuartusII development environment,each module is designed and the waveform is observed with ModelSim.The UDP/IP protocol stack and 10 G MAC controller download the program to the FPGA hardware platform.By testing the MAC controller between the FPGA and PHY chips,the 32 bit width data interface is realized.Each can implement 312.5bit/s,and have a complete data format,verify the transmission bandwidth of 10Gbit/s,verify the image acquisition and storage module,and verify the real-time performance of the video image by the FPGA connection VGA interface.