Research On IP Core Design And Verification Technique

With the development of science and technology, semiconductor manufacturing process enters into Very Deep Sub-Micron era. It is possible that integrates more than million transistors into a single chip. IC (Integrated Circuit) design industry and manufacturing trend to integrate with the quick development of integrating technology, and SoC becomes the main trend. Nowadays chip vendors aim at area minimization and function maximization. In despite of SoC being provided with many merits, much new challenge of IC design and verification is brought by it.The thesis discusses SoC bus architecture, the integration and reuse of IP, and SoC verification methods. Microcontroller soft IP design and verification is given as a typical example. The main work and achievements are as follows:1. The thesis introduces the key technique of SoC design and verification. The challenge of SoC design and verification, the integration and reuse of IP core, the reuse of verification IP and function verification automation are discussed in detail.2. A 8-bit RISC microcontroller soft IP is designed, which belongs to SoC. First the architecture, instruction set design and timing and pipeline design of the soft IP are described in detail. Second each functional module design is introduced.3. Some verification methods, used in ASIC circuits usually, are analyzed, which are compared with SoC verification methods. SoC verification is more focused on the interface between IP cores. Considering SoC size and complexity, a verification platform of reuse and automation is designed to reduce the complexity of SoC verification.The soft IP acts in accordance with VSIA (Virtual Socket Interface Alliance) criterion, and hierarchy bus and interface standardization are characteristic of the soft IP, which is verified on the verification platform mentioned above paragraphs. As a result, the latter is more efficient than traditional verification method, and achieves the objective of reuse and automation.