PCIe Module Verification Based On An Automated Verification Platform

With the upgrading of the smart phone market,the performance of smart phones in the new era has been greatly improved,which also puts forward higher requirements on the internal data interface of the mobile phone chip.The PCIe data interface module studied in this thesis is an important bridge port for data interaction between the base-band chip and the application processor chip.Due to its high bandwidth and strong anti-interference capabilities,it satisfies the current smart phone market's demand for data interaction interfaces.In order to ensure that the PCIe data interface module can work stably at high speed in the chip,it needs to be fully verified in the research and development stage of the project.At the same time,in order to get the product to market as soon as possible,so as to occupy a favorable position in the market,it is necessary to further improve the efficiency of the verification work,thereby shortening the research and development cycle of the project.The factors that affect the efficiency of module verification are mainly the construction of the verification platform and the coding and debugging of test cases.When building a verification platform for the PCIe data interface module,the data incentive input the design must conform to the data form stipulated by the PCIe protocol.As a result,when using common UVM verification platform construction methods,verification engineers need to spend a lot of time to understand the characteristics of the protocol and complete the implementation of complex data incentives,it will consume a lot of human resources and reduce verification efficiency.And when coding and debugging the test cases,the inconsistency in the style of the test case data excitation sequence codes used by different verification engineers will reduce the re-usability of these commonly used excitation sequence codes and affect the later test cases debugging,thus reduce verification efficiency.Therefore,when the PCIe module verification platform was built,this thesis combined PCIe VIP technology and used Python-based automation tools to reduce the time to build a complex incentive model for the verification platform.At the same time,this thesis completed the design of the standard instruction sets which can be combined into different test cases,these standard instruction sets can greatly improve the re-usability of theexcitation sequence code.After comparing with the traditional projects in the past,it was found that the time period for setting up a traditional PCIe verification platform was about7 days.However,through the automatic verification platform generation process described in this thesis,it took only 1 day to complete the construction of the verification platform and the time was reduced by 86%,greatly improving the efficiency of verification.Not only that,through the rational application of the standard instruction set,the time taken to complete the test case of basic functions such as register access and link up was reduced from 10 days to 3 days,and the time was reduced by 70%.The verification efficiency had been greatly improved again.After completing the construction of the PCIe verification platform,this thesis firstly completed the key verification function points by analyzing the module design documents.Then it also designed corresponding test cases for each function point and completes the corresponding simulation.And,by collecting the optimized coverage report,it was found that both the code coverage and the function coverage reached 100%.Finally,by completing the actual rate calculation and analysis of the PCIe module in two rate modes,it was also found that the actual rate in GEN1 mode was 2.26 Gbps and 4.42 Gbps in the GEN2 mode.The final verification result both met the requirements of the PCIe design specification.