Design Of Multi-Core NoC Platform Based On FPGA

The continuous advancement of semiconductor technology,and the increasing attention to energy efficiency,have led to an industry-wide shift in focus towards the design of multi-core parallel processing in order to meet performance goals.In the traditional system-on-chip,when the numbers of processing cores was relatively small,researchers used bus-based or point-to-point connections as global interconnection networks.When processing cores are increased and applications with large traffic are faced,the disadvantages of these methods are: low communication efficiency,poor reusability and scalability.Therefore,Networks-on-Chip(NoC),a new type of inter-core communication method,is widely regarded as a promising approach to solve the communication needs of large-scale Chip Multi-Processors(CMPs).In these thesis,an FPGA-based multi-core NoC hardware platform was proposed and verified to be applicable to the acceleration of parallel algorithms.The core work of the dissertation consists of the following three parts:(1)The design of NoC.This packet-switched on-chip interconnects can be embodied by many routers that are connected to each other in a peer-to-peer manner.The design of the NoC is characterized by three main design parameters.?1 Topology: The topology determines the number of routers and links and how they connect to each other.And the topology establishes basic boundaries for the overall energy efficiency and network performance.?2 Routing:The routing algorithm determines the path of a given data packet from the source to the destination.It affects the average number of hops and the load balancing between the network links.?3 Switching: The switching is used to manage how routers communicate with each other.It determines when a data packet can be sent from one router to the next.Then,based on the comprehensive consideration of network performance and hardware implementation,we design NoC with the 4*4 Mesh topology,XY dimensional routing,and the wormhole virtual channel switching.(2)The design of Reduced Instruction Set Computer(RISC).The processing unit for multi-core platforms needs a great deal of flexibility,which is conducive to the smooth upgrade of the system without replacing the hardware,thus reducing the costs;at the same time,the processing unit needs to exchange data efficiently with the NoC network interface.Based on the processor design software Processor Designer,we designed a RISC processor to meet the above requirements.The three key elements of processor design are: the hardware architecture and software architecture of the processor,the design of the processor instruction set,and the design of the processor pipeline.In this thesis,we designed a reduced instruction set processor based on Harvard architecture and MIPS five-stage pipeline.(3)The applications on the multi-core platform.we show the mapping and computing process of the BP decoding algorithm of polar code which demonstrates the superiority of multi-core platform when implementing parallel algorithms.