Parallelization Implementation Of SAR Radar Algorithm On NoC-based Multi-core Processor

Now traditional single-core processors can’t meet the performance requirement of complex data operations in modern digital signal processing. With the appearance of multi-core technique, the development of processor has been raised to a new step. Network on Chip (NoC) technology is a strategic technology of integrated circuit design nowadays, and also a research focus in the field of integrated circuit. The core idea of NoC is migrating computer network communication technology to chip design in order to replace the traditional SoC bus communication architecture. NoC has extreme advantages in scalability, reusability, design efficiency, which have made it one of the most promising solutions of the communication problems on chip.After extensive reading of a large number articles of NoC, we firstly classify, summarize and compare the current various designs of the NoC. Then based on the theory of NoC Design Space, we analyze some key technologies of NoC, include network topology, routing algorithm and flow control.Design of application-oriented approach requires a detailed analysis of the characteristics and needs of the application. Synthetic Aperture Radar(SAR) algorithm,as a typical modern mathematical signal processing algorithm,has the features of large amount of complex data calculation and frequent data communication.Traditional DSP processors can’t meet such complex data progress in terms of function or performance.So it is the most direct and easy to explore parallel processing method on a new platform.After the analysis of the main steps of the two common SAR imaging algorithm(RD and CS) based on parallelization partition granularity,we explore the possible impact on SAR algorithm efficiency if we choose different partition granularity.An important basis of the hardware architecture and functional design is the characteristics and needs of the application.In the passage we detailed analyze how the hardware design of the SAR imaging algorithm demo system meets the characteristics and need of the SAR imaging algorithm,which focuses on the design of data computing module—the coprocessor design.Finally,based on the concept of Hardware and software co-design simulation, we establish a parallel system-level simulation platform for the hardware structure of the demonstration system, the functional modules and SAR radar algorithm processes with object-oriented design methods. It is quite useful for the parallel division of the algorithm and the whole hardware and software debugging.And we propose a hybrid parallel scheme and give a complete parallel method for RD algorithm. The experimental result on FPGA demo system shows that this parallel method is reasonable,accurate and effective.