Comprehensive Design Of Arbitrary Ratio Resampling And Timing Correction In Parallel Architecture

With the rapid development of the information industry,the broadband signal transmission promotes the stronger requirements,which brings great challenges to the hardware process in terms of traditional serial structure.By the research on the traditional timing synchronization architecture,this thesis presents a high-rate timing correction loop scheme suitable for multiple modulation signals based on the APRX parallel demodulation architecture.The scheme designs parallel arbitrary ratio resampling,parallel frequency-domain matched filter and parallel timing correction loop as the main link,and combines the phase correction and frequency compensation double feedback loop to complete the comprehensive design of arbitrary ratio resampling and timing correction in parallel architecture.Through the digital resampling theory,the thesis designs a Farrow-based polynomial interpolation filter.With the on-line time-varying interpolation coefficient calculation,the filter realizes the integer times symbol rate from an arbitrary sampling rate.The designed algorithm covers the interpolation filter,resampling controller and timing adjustment.Taking into account the characteristics of high-rate data,the thesis uses the mathematical relation of time-frequency domain to design the most optimal matched filter in frequency domain,meanwhile designs an 8-based 64-point parallel Discrete Fourier Transform.According to the above algorithm,a parallel timing correction loop associated with symbol rate recognition is proposed.The loop consists of two parts,one is to study the symbol rate and the phase offset estimation algorithm,the other is the design of a dual feedback loop algorithm that combines frequency-domain matched filter for phase offset correction and combines arbitrary ratio resampling for frequency offset compensation.Finally,the thesis completes the test and verification above modules on the hardware platform.The results show that this design can support 400 MHz wideband,20~360Msps symbol rate,720 MHz IF 8PSK,16 QAM,32APSK and other modulation signals.The timing correction loop can accurately obtain the maximum SNR symbol data,and make signal vector magnitude error below the 10% rms specification requirement.