Study And Implementation Of Synchronization For Parallel High Data Rate Demodulation System

With the popularization of information technology,modern communication technology is developing towards the direction of high-order modulation and high-rate transmission.It brings a great of challenges to the communication testing industry meanwhile.How to measure the quality of complex modulation signal accurately is an urgent problem to solve for communication testing industry.For designing a high-rate and multi-standard communication demodulator,we analyze the key techniquies of demodulator such as parallel constructure for signal timing & carrier synchronization in the way of theoretical analysis and algorithm research in this thesis.Above all,the thesis analyzes the specifications in design requirements,including the signal bandwidth,transmission symbol rate,baseband match filter and others.Then,a scheme of 32 parallel demodulation system appling to MPSK,MQAM and MAPSK is proposed and describled in detail.Furthermore,through the comparison of the M&M,Gardner,O&M,early late gate algorithm etc.,the thesis finally chose s the O&M to be the timing estimation by its hardware simplicity.,For the high-rate timing error estimation and correction the thesis deduces a parallel structure based on the Fourier transform.Moreover,the simulation by MATLAB shows that the O&M algorithm is independent of the carrier synchronization.Additionally,based on the decision feedback mechanism,the thesis proposes a parallel carrier synchronization architecture to meet the requirements of multi-modulation mode and high-rate demodulation.Then,the thesis designs the algorithm for each modulation format,discusses the loop filter and the numerical control oscillator.The simulation indicates that the algorithm can cover the MPSK,MQAM,MAPSK signal demodulation with a large range of frequency offset.Finally,the thesis develops a high-rate demodulator with the field programmable gate array(FPGA)by the proposed architecture and algorithms.The experiment results show that,the timing synchronization loop can obtain a maximum SN R of symbol data;the carrier synchronization loop can achieve the requirement of ±10k Hz~±1MHz frequency offset.