Research And Implementation Of Digital High Speed Parallel QPSK Demodulation Technique

With the rapid development of space science and technology and to continue to explore space, the wireless communication data transmission speeds higher and higher, and for real-time and error rate of transmission equipment have become increasingly demanding. Domestic space technology is still relatively backward, and can not achieve high-speed satellite image data transmission requirements, it is essential to study the wireless data transmission system. Modem technology is the core technology of high-speed wireless communication difficulty and is currently the data transmission system research. When the baseband data rate is relatively high, the demodulation side will need to deal with more high-speed serial data directly running demodulation algorithm requires a digital chip has rich resources and relatively high operating clock. The current commonly used digital chip FPGA internal operating clock over 400 MHz when it is prone to errors, complex demodulation algorithm for parallel processing in order to meet the need for high-speed data transmission.In this thesis, all-digital high-speed parallel QPSK demodulation technology hardware research. First, analysis the demodulation principle of detailed and formula derivation, which includes digital down conversion, carrier synchronization, loop filter, numerically controlled oscillator, transversal filter based equalizer and the like. Data followed by the derivation of the basic modulation and demodulation algorithm available down conversion and low-pass filter in the demodulation process requires processing operation at most, and most of the data using multiplication. Multiplication will spend a lot of resources and seriously affect the demodulation speed, in order to achieve high-speed demodulated output, we need a parallel filter to achieve fast data processing. Paper introduces the CIC filter, parallel time domain filter, analyze the advantages and disadvantages and scope of the trial of two filters. And through the discussion of the linear convolution and circular convolution theorem proposed using correlation and FFT fast convolution algorithm for parallel frequency domain filtering, which parallel the frequency domain filtering generally adopt two ways: linear convolution-based the overlap-add method; with overlapping circular convolution-based retention method. Then QPSK modulation and demodulation of the basic principle of modeling and simulation by MATLAB / Simulink platform, using Simulink tool oscilloscope, spectrum analyzer,signal source modules for functional verification simulation model to calculate the critical parameters for hardware implementation. Finally, a program written in Verilog hardware parallelism demodulation hardware system real-time testing and analysis, by observing the signal spectrum, eye diagram, constellation diagrams show that the use of FPGAscale exchange processing speed, which can achieve high-speed signal demodulation and data transfer, and the entire hardware design and implementation is relatively simple, has a relatively high demodulation performance.In summary, through the high-speed parallel QPSK modulation and demodulation and other relevant principles of research and analysis, the use of MATLAB / Simulink modeling and simulation program written in Verilog hardware online real-time testing and analysis, test results show that FPGA-based high-speed parallel demodulation techniques You can reach the relevant target, greatly improved the hardware demodulation rate of future research has a very important significance.