The Circuit Design And Implementation Of New Charge Trapping Memory

With development of the digital technology wide applied in the mobile communication, data terminals, multimedia and consumer electronics, Flash Memories have play an important part in SOC, and hold a significant position in semiconductor industry. However, as technology continues to improve, and people are increasingly demanding product high performance, the traditional floating gate memory is restrict in some aspects lead to inevitability of developing charge trapping memory of the next generation. Since CTM technology in china is still in the early stages of development, therefore, there is great scientific and economic value to do more researches on charge trapping technology and embedded systems.According to the operating characteristics of the charge trapping cell, and referring to the datasheet of Numonyx₆5nm₃V₂Gbit, the capacity of 1Gbits NOR structure of flash memory system architecture is proposed. In addition, the high performance read path to design for 1Gbits charge trapping memory. Furthermore, Design and optimize the sense amplifer, charge pump system generation and management module, level shifter and bandgap reference, and other related circuit. Finally, based on SMIC's 65nm process, the layout of the charge trapping memory array architecture and peripheral circuit is given; layout problems encountered during layout have been researched.Based on SMIC 90nm'spice model to design this embedded CTM memory. For the new structure of the sense amplifier, the simulation results show that the sense time of the new structure of sense amplifer is 4.5ns in the worst case; in general, the sense time is less than Ins. With the function of programme, read, erase by sector and soft programme, require the system's access time programming time and sector erasing time for this system is less than 100ns,5μs and 100ms.