Design Of Deep Storage And Time-interleaved Sampling Mismatch Compensation For Portable DSO

As a general standard equipment,digital storage oscilloscope(DSO)has been widely used in various signal measurement.As a branch of DSO,portable DSO has overcome the disadvantages of normal DSO,such as large-volume and non-portable,and it has been widely applied in some situations.In terms of sampling rate,the single analog-to-digital converter(ADC)cannot maintain a high sampling rate while ensuring high resolution due to the limitation of current semiconductor technology and cost performance.In order to improve the system sampling efficiency,a time-interleaved sampling technique based on multi-slice ADC parallel array is proposed.In terms of data storage,storage depth not only restricts sampling time of the system,but also limits the maximum length of continuous sampling signal.Therefore,in order to improve the maximum time of DSO in continuous sampling mode,a deep storage technology based on SDRAM is proposed.In the time-interleaved sampling design,we propose a improved set of methods for compensating the distortion created by mismatches in the time-interleaved analog-to-digital converters(Time-interleaved ADCs).The error compensation of offset and gain is realized by error parameters,and the error compensation of sampling time is realized by the simplified Lagrange interpolation algorithm.The compensation method is implemented in FPGA with the low complexity of fixed-point algorithm,and the online calibration of dual-channel ADC sampling data is implemented in the TIADC hardware platform.The experimental results show that the proposed method improves the spurious-free dynamic range(SFDR)of sampling data up to 51 dB in the simulation environment,and it optimizes the SFDR up to 45 dB in the process of hardware implementation.Under the premise of maintaining the error estimation precision and compensation effect,this method not only reduces the computational complexity of the algorithm,but also the compensation structure is not limited by the number of TIADC channel.In the deep storage design,a design scheme of deep storage controller based on FPGA+SDRAM structure is proposed in this thesis,which realizes the depth storage of sampled data,and the storage depth is up to 8MB.Besides,the FIFO input/output cache module is used to solve the data loss problem of SDRAM in the automatic refresh operation,and the feasibility of the design is verified by the simulation platform under the condition of the 100 MHz clock frequency.In the power management design,the power management system with discharge protection is designed in this thesis,which realizes the functions of charge and discharge management of lithium battery,load power supply management and power state information monitoring based on UART bus.