In Multi-chip Ad Parallel To The Research And Implementation Of The Data Acquisition Technology

With the development of modern radar and communication systems, the data acquisitionsystem need work at higher sampling rate and precision. Limited by ADC chip's manufacturingprocess, It is hard for a single ADC chip to acquire the high sampling rate and precision Theparallel times-interleaved sampling ADC system is an effective way to increase the sampling rate.The time interleaved ADC system works as: M parallel ADCs work with a samplingfrequency fs / M and the system output are multiplexed together. This gives an overall samplingfrequency fs . The drawback with this structure is that, the channel mismatch errors will occur inthe system. The mismatch errors mainly include time errors, gain errors and offset errors. Thismeans that the signal will be non-uniformly sampled. These mismatch errors will degrade thesystem performance if they are uncorrected.This paper gave an explicit analysis of such three channel mismatch errors. We establishedthe formulas of spectrum when all three mismatch errors exist together. We presented the measureerrors algorithm combined three errors according to the formulas of spectrum and the effectivecalibration algorithm based on FARROW structure. The algorithm was implemented in a FPGAchip at last.The primary works in this paper are presented as follows:1. The creative and useful algorithm was presented to measure and calibrate the three mismatch errors by explicitly analyzing the three mismatch errors in time-interleaved sampling system..2. To complete the parallel data acquisition system with 400M sampling rate made up of two AD94303. To complete the system performance analysis according to simulation and test.