| Analog to digital converter (ADC) is very important in signal and information processing system. With the development of wide band radar technology and the software radio, it is more and more important for an ADC with higher sampling rate and higher precision. Limited by ADC chip's manufacturing processing, it is hard for a single ADC chip to acquire the high sampling rate and high precision at the same time. The method of parallel times-interleaved sampling ADC system is effective to solve this problem.In the time-interleaved ADC system, M pieces of ADCs work, in a parallel method and sample at a sampling frequency f_s/M , in the back-end of the system, M outputs are multiplexed to give an overall sampling frequency f_s. The drawback of this structure is that ADCs are not exactly identical due to errors in the manufacturing processing. This means that time, gain, and offset mismatch errors are introduced in the ADC system. These mismatch errors will degrade the system performance greatly.In this paper, we analyzed the reasons generating the channel mismatch errors, established the formulas of spectrum including three mismatch errors, and presented the algorithm measuring the three errors and corresponding calibration method. At last, we proved the availability of the algorithm by simulation. Combining with theoretical analyses, we designed and constructed a high-speed and high-precision data acquisition system working at 200 MHz sampling frequency. The test indicates that it can improve the performance of the system.The primary works in this paper are as follows1. Analyze the channel mismatch errors, present the method to measure errors and calibratealgorithm based on the error values. Finally, we simulate and analyze measurement and calibration algorithm.2. Complete the parallel data acquisition system made up of two AD6645 with 200 MHzsampling frequency.3. Analyze the performance of the algorithm mentioned above according to the simulationand the test results. |
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