Research And Development Of CMOS Monolithic Integrated Photoreceiver For Optical Access Network

Optical transceiver,in particular,photoreceiver as the core part of optical access network system,has become a hot research.At present,photodetector(PD) mainly are hybrid integrated with transimpedance amplifier(TIA).The realization of monolithically optoelectronic integrated circuit(OEIC) chip of PD and TIA by the standard CMOS technology,which has better performance and lower cost,will have very good market prospects.The subject of this paper is to achieve the optoelectronic-integrated photoreceiver applied in 850nm fiber-optical access network of 10M/100Mbps, namely,the successful monolithic chip of PD and TIA used in 850nm optical fiber communication is accomplished.In this paper,the following work is finished:1.Two kinds structure of photodetector,Double Photodiode(DPD) and Spatially Modulated(SM),are designed for 10M/100Mbps transmission.Then the basic principle of PD is introduced and the establishment of device circuit model is finished. Based on those,the bandwidth and DC response of PD are simulated.2.The various types of pre-amplifier are discussed,and Transimpedance amplifier with RGC structure is selected.To improve DC responsiveness of the DPD and the SMPD,the secondary broadband amplifier is designed.3.Cadence software is used to complete the OEIC chip layout and chip is fabricated by 0.5μm CMOS technology in CSMC technologies corporation.4.OEIC chip is packaged on ROSA type,and its small signal bandwidth is tested, the signal transmission rate and the DC responsiveness of DPD-OEIC are also test.The DPD-OEIC chip using ROSA package replaced the existing ROSA in the optical transceiver business of 10M7100Mbps.Transmission rate is tested for 72Mbps. So it can be applied in 10Mbps data transmission but can not be applied in 100Mbps. The SM-OEIC chip is forecasted to apply in a higher rate transmission.The innovations in this article are introduced as follows:1.The PD+TIA chip is designed under monolithic optoelectronic integration in standard CMOS process,and the OEIC chip with ROSA package can be applied in 72Mbps data transmission.2.The DPD and SM-PD are designed,and the novel device circuit model is built in order to achieve the overall OEIC simulation in the Cadence and the overall layout.