Simulation And Design Of CMOS-Process-Compatible Optical-Electronic Integrated Detectors And Receivers

Optical communications is one of the cornerstones of today's revolution ininformation technology. Optical receiver takes an important part in opticalcommunications system. To achieve high speed and high volumes in opticalcommunications, optoelectronics integrated circuit (OEIC) is the ultimate way,because OEIC eliminates the parasitic effects induced by hybrid integrate. Thistechnology also has advantages of reducing chip area, achieving higher yield andhigher reliability. To achieve CMOS-Process-Compatible OEIC receiver, a high speed and lownoise Photo-Detector and a high gain, large bandwidth amplifier are required. So wedesign a DPD (double photo-diode) detector and a RGC(regulated cascode)TIA(transimpedance amplifier) for the OEIC receiver. The main research work in the paper includes:1,Design of CMOS process-compatible photo-detectors. With the help of device simulation this paper analyzes the mechanism of photo-generated carriers' transmission delay and gives the equivalent circuits of the DPD under high frequency.2,Design of OEIC receiver. We have designed an excellent TIA and applied computer-aided design software to optimize it. Also, the DPD and the circuit were co-simulated in one environment. The gain and -3dB bandwidth of the RGC TIA are 54.5dB and 2.04G, separately. The OEIC receiver can work well at the bit rates of 1.25Gbit/s.3,Implement and test of the design. The design was taped-out in Wuxi CSMC's 0.6μm mixed-signal CMOS technology via ICC's MPW. We got some good test results: the dark current is less than 10pA, the barrier capacitance is less than 1.89pF, and the responsibility is 0.0366A/W.