Research On Timing Analysis Of Digital IC With NBTI Effect Considered

With the shrinking of CMOS technology,the Negative Bias Temperature Instability(NBTI)has become one of the significant impacts on the reliability of VLSI circuits.Accurate device degradation model is a prerequisite for high performance and high reliability integrated circuit design.Based on 45 nm CMOS technology,the shifts in propagation delay of various logic gates caused by NBTI have been simulated,investigated and modeled.The proposed models have been applied to the analysis of NBTI degradation of benchmark circuits(ISCAS85).The main work and research contents are as follows: 1.The gate level degradation model of digital circuits under the influence of NBTI has been established in two different ways.The tranditional NBTI degradation model of transistor level is used to calculate the threshold voltage drift of PMOS devices under various conditions.Two different modeling methods have been adopted.The first way is based on surface fitting: by segmenting the simulated data,the three-dimensional models have been established one by one,and then all of them are further combined to get the four-dimensional degradation model.The other method invovles the using of neural network: according to the propagation delay characteristics of logic gates,the neural network BP algorithm is used to train the sample data,and then the propagation delay models of seven fundemental logic gate circuit have been built up.2.A calculation framework of logic gate degradation,which is used to calculate the path dealy of combinational circuit,has been proposed.Furthermore,we have coded the proposed calculation framework in which the gate level degradation models proposed above have been embedded.Thus,the propagation delay caused by NBTI degradation of the combinational circuit is obtained.3.We have also programe the calculation method to filter out the potential critical path in combinational logic circuits.All the potential critical paths induced by the NBTI effect can be found out.The method can be applied to various combinational circuits to achieve their characterisitc of NBTI degradation.All above research results are desired to be references for modeling of NBTI effect and reliability design of VLSI circuit.