Research On Spectrum Sharing Strategy In Utility-based Cognitive Radio Networks

Manufacturing technique has made great progress with the development of integrated circuit.But IC design capacity cannot keep pace with the level of manufacturing ability.The "price scissors" between both seriously restricts the IC's further development,so system on chip design concept which adopts modular method is on the agenda.It becomes the mainstream for high efficient and short time to market features by reusing mature intellectual properties.Integrating a large amount of IPs on one chip also brought great challenge for testing and fault diagnosis.First,IP's diversity means users need employ a great variety testing methods and embedded measure means users lost the control and observation of IP's primary ports.So a large of extra logics are inserted to increasing circuit's controllability and observability,which brings hardware overhead.Further,it makes the fault diagnosing mission even more difficult.The paper carries research on the following topics to fix problems described above.Firstly,doing SoC design integration work for test based on scan design and LBIST design.Four dimensions including high reliability,hardware overhead,test pattern generation time and automatic test equipment's(ATE)capacity are elaborated to analyze the necessity of integration.And feasibility study of circuit structure is done based on Mentor software.The hybrid TK/LBIST flow is implemented in engineering practice which can effectively reduce hardware overhead,time for pattern generation and memory of ATE.Secondly,doing research on scan test architecture of IP embedded on SoC.After analyzes the two typical architectures:long-chain architecture and chain-compressed architecture,the paper improves scan test structure by three steps.In first step,concatenates short chain under same clock domain before compressing to alleviate the complication of compression logic.In second step,adopts IP bypass mechanism to isolate IP chains by using a group of single register.In third step,integrating the two architectures vastly enriches testing strategies.Practical application proves its flexible.Finally,aimed at the problem encountered in simulation process,an simplified isolation structure referring IEEE 1500 is put forward which can largely reduce verification effort.Thirdly,doing research on chip's fault diagnosing when taped out.An at-speed fault diagnosing method based on scan chain with compression logic is proposed in this paper.By combining test on ATE and software diagnosis,the diagnosing flow is implemented on a taped-out SoC chip,which proves that the method is effective in faults diagnosis and faults location.It can accelerate the convergence of ATE test debugging flow.Furthermore,analyzing chip's frequency-voltage shmoo picture and doing diagnosing work on fault nearby critical value picked out,can guide the next similar generation chip's frequency improving.