Fault simulation and multiple scan chain design methodology for systems-on-chips (SOC)

Pre-designed functional blocks, called intellectual property (IP) cores are being widely used for cost-effective and timely design of systems-on chip (SOC). In current SOC test methodology cores are tested using pre-computed test vectors provided by core vendors. Scan-based DFT (design for testability) approach is widely used to apply pre-computed test vectors. This dissertation presents a SOC fault simulation methodology that protects core IP and a novel multiple scan chain design framework.; Reuse of pre-computed core-level tests protects IP, and reduces test development effort. However, such advantage comes at the expense of high hardware overhead, test application time, and performance penalty. In contrast, if a soc vendor can select SOC-specific multi-phase test methodology test application cost reduces drastically. We collectively call the tests used for multi-phase testing a custom test set. Currently, development of custom tests for a SOC is possible only if the netlist of each core used in the SOC is available.; We have developed a new test development framework that protects IP as completely as the current approach while also allowing efficient development of SOC-specific custom tests. In the proposed, each core's netlist is retained on computers controlled by the core vendors. The SOC vendor generates tests efficiently by interactively querying a set of procedures running at each core vendor's computers. Under this paradigm we developed a distributed fault simulator for both full scan (combinational) and sequential SOCs that is efficient and protects core IP. Accuracy of the proposed fault simulator is identical to that of a traditional fault simulator for any given system level tests. However, unlike a traditional fault simulator, the proposed fault simulator does not require the netlist of the core to be revealed to any SOC designer. We also showed that we are able to perform efficient fault simulation revealing only core input-output dependency and logic behavior. Parallelization techniques are developed to reduce impact of communication latency.; DFT enable the quality goals to be met with a high degree (high fault coverage) during test, allow the coverage measurement to be done efficiently and economically, and help ATPG process. This dissertation addresses the issues of high test application time and hardware overhead associated with scan-based DFT in SOC designs. We describe multiple scan chain design framework that optimizes test application time and routing overhead in an integrated manner. This is a branch-and-bound approach for designing non-reconfigurable, and reconfigurable multiple scan chains. Several circuit properties and bound computation techniques are developed to reduce time complexity and search space. Experimental results demonstrate significant reduction in test application time and hardware cost over prior heuristic approaches. In realistic time complexity the search procedures design scan chains with test application time within two times of the global optimal.