Developent Of Boundary-Scan Test And Fault Diagnosis System

The package of new electronic components is developing thin and integrated, traditional test equipment is difficult to adapt. the boundary-scan technology came into being, which works with the virtual probe pre-builted in the circuit chip testing working status of digital circuits under computer controlling. Considering the fact that nowadays most CPLD, FPGA, MCU, DSP and other important components which are widely used in digital circuits have supported the function of boundary-scan, as well as the trend of digitalization of electronic equipment, this paper brings forward and realizes a kind of boundary-scan test and fault diagnosis system based on virtual instrument after analyzing the new features of digital testing, hoping to provide a general and effective tool for the testing of digital system.The boundary-scan test system consists of PC computer software and JTAG controller. On the basis of analyzing IEEE Std 1149.1-boundary-scan test theory, this paper discusses testability theory, DES theory, fault diagnosis algorithm, SVF standard used in boundary-scan test, to complete generating and loading of testing vector, saving and analyzing of testing response using PC host, in order to complete the analysis of measuring object and implement the whole testing process of integrity, interconnection, function and cluster.The focus of this study and system development are functional testing methods and connection testing. The core issue is to establish testing of test vectors TPG and expected response ORA, as the basis for the full realization of the interconnection wiring circuit board-level testing, on-chip functional test and cluster no-boundary scan device testing. Software interface is designed from the user point of view, not only giving the test results also able to demonstrate the testing process, and the general users of the system who just understand the basic concepts of boundary-scan test and does not need to understand the specific internal details, use the boundary-scan test technology for the actual circuit testing. Design for testability first define the fault model, and then set up the testing process and test results to reflect the events of information collection, and the simulation results and analysis of failures and events which reflect the characteristics of relationship matrix. Then finalize the specific fault. In this research and development, the controller uses the parallel port and USB virtual instrument simulation in two ways. The former using PC parallel port download cable configuration, and then develop software to simulate the underlying JTAG work; while the latter, exchange information with USB interface, and performe an independent boundary scan through low-level module with its own keyboard and LCD display process.This paper chooses FPGA07 and LG06 as two typical tested objects. The application examples of testing the two boards illuminates the boundary-scan test system's using method and testing process, also shows the demonstration flow of digital system's full boundary-scan test process.