The Research And Design On Low Power SAR ADC With High Speed And High Resolution

ADCs are the interface between analog and digital world, which are also the key modules of modern electronic systems. Compared to traditional high speed high resolution ADCs, SAR ADCs have advantages on low power and small die area. Moreover,with the absence of linear analog circuits, SAR ADCs are more adaptive in modern integrated circuits(IC) process with better integration of digital circuits, which can have higher sampling rate and resolution under new processes. As a result, SAR ADC can satisfy the requirement of many electronic devices, such as radar, telecommunication, measurement, observation and control, instruments, and etc, which also have wide prospect of application in low power system on chip(SoC) design and mobile equipments. Thus,SAR ADCs are one of the major research area in analog to digital conversion.To improve the performance, this dissertation analyzes the system structure and limitations of key modules of SAR ADCs, including comparator noise and offset, comparator power and speed, DAC noise and linearity, DAC switching scheme with power and complexity, DAC sampling and settling errors, control logic structure and speed, metastability errors.This dissertation focuses on the design of high speed low power SAR ADCs and high resolution low power SAR ADCs, covering system structure, error calibration, speed and power optimization and circuits implementation.The specific research contributions for high speed low power SAR ADCs include:(1) A noise and offset tolerant model is proposed with static or dynamic offset and noise tolerance which improves 12% quantization speed with only 15.5% power increasing.(2) A new DAC-based offset calibration technique is proposed with noise averaging which limits the offset error to 1 bit without increasing comparator power or slowing down comparator speed.(3) A new hybrid pipeline-SAR ADC architecture is proposed with 30% speed enhancement and the absence of high power low linearity opamp.(4) In circuits design, several new circuits are introduced: a noise and offset adjustable dynamic comparator with 50% dynamic offset reduction; a high speed low power NMOS input single stage dynamic comparator with 8% speed increasing and 20% power reduction; a new high speed asynchronous control logic with meta-stability reduction and only two-inverter logic delays; two new self-design high linearity DAC layouts with less than 0.6% mismatch which can satisfy 11 bits SAR ADC; a common-mode stable Virtual Merged Capacitor Switching DAC switching scheme with 95% power reduction and the absence of external common-mode voltage.According previous models and circuits, 3 SAR ADCs are designed. A 10-bit50MS/s prototype SAR ADC is implemented in 130 nm CMOS process. Test results show 1.09 mW power consumption, achieving 8.9-bit ENOB and 46fJ/conv FOM at low frequency, 8-bit ENOB and 87.6fJ/conv FOM at near Nyquist frequency. Another 10-bit100MS/s prototype SAR ADC is designed in 65 nm CMOS process with 9.4-bit ENOB and 1mW power dissipation post simulation results, achieving 15fJ/conv FOM. An 8-bit500MS/s hybrid pipeline-SAR ADC is also designed in 65 nm CMOS process, schematic simulation shows 7.49-bit ENOB and 1.53 mW power consumption, achieving 17fJ/conv FOM.The specific research contributions for high resolution low power SAR ADCs include:(1) Several new DAC switching schemes are proposed, achieving more than 95%DAC power reduction and 1 bit linearity improvement through reducing capacitor switching frequency at maximum error point.(2) A new no redundant DAC mismatch calibration model with offset and noise reduction is proposed. By adopting zero differential inputs to measure the offset and mismatch errors, along with noise averaging, this model uses different number of small capacitors to compensate for mismatch errors. The average ENOB of SAR ADCs after calibration is 10.9-bit with 2 bits accuracy enhancement.(3) A signal independent DAC mismatch adaptive digital calibration algorithm is proposed. Errors are measured by two calibration signals generated and subtracted on DAC, which are minimized by Least-Mean-Square(LMS) algorithm through modifying the coefficients of transfer function. After calibration, the average ENOB is 11-bit with20000 samples convergent time and 4 bits accuracy enhancement.