Research And Design Of L2 Cache Based On PowerPC Architecture

For microprocessors,the capacity of cache unit(L1 Cache)due to its location and function which maintain approximately equal to the frequency of the processor will not be very large,which increases limitly performance of processor.Processor has to access the main memory each missing which is very long about even thousands of times when not used L2 Cache.So the lack of cost of the processor is very large,resulting in a large delay in the average visit,and the performance of the upgrade is very limited.So,it is very critical to upgrade the performance of processor that using the appropriate L2 Cache to reduce the miss rate.Power PC Architecture with its advantages of high performance,low power consumption and high stability in industrial control,communications,defense aerospace and other fields is widely used.This paper designs and implements an L2 cache based on the Power PC architecture of the processor IP core,aggregate requirements,application scenarios to reduce the number of processor misses and excessive latency in the event of a loss,greatly reducing the processor's average access latency.Based on the Harvard architecture of the L1 Cache in Power PC processor and easy to implement,L2 Cache used a unified storage approach.Storage and Controller is the main two parts of Cache.The Storage part consists of SRAM,which is divided into Data SRAM and Tag SRAM;The controller section is responsible for the hit judgment,allocation and data validation of the request.Firstly,this paper studies the principle,influencing factors,structural design and L1 Cache of Power PC,and summarizes the methods and points of L2 Cache in design.The performance of L2 Cache is influenced by storage methods,implementation,capacity,block size,relevance and replacement algorithms and other factors.Power PC Architecture research mainly on its cache unit(L1 Cache)to study,which use of separate 32 KB instruction Cache and 32 KB of data Cache,and the frequency of L1 Cache with the same as Power PC Architecture.Secondly,according to the project requirements and preliminary theoretical research put forward specific design.The Storage part used design of the Von·Neumann structure of the storage system,4-way set associative mapped,256 KB of Data SRAM,24 KB of Tag SRAM and serial access.The Controller section is mainly done by the Cache-Controller module and Access controller part.Cache Controller module includes cache control,pipeline design,the least recently used replacement algorithm and parity logic,which responsible for the judgment of the hit,the allocation of the request,the choice of the best alternative pathways and parity judgments.The access controller includes the instruction cache read operation,the data cache read operation and the data cache write operation.To prevent the current request or missing request to block the pipeline,add data-cache and instruction-cache read queue implementated by a FIFO which depth is 4,and data-cache write queue implementated by a FIFO which depth is 2,when missing support for four pending requests.In addition,also used the design of priority management and three independent pipeline to optimize performance.Finally for the verification phase,mainly from several major functions to verify and analyze.After verify,the function of L2 Cache to meet the design specifications,so that the average access latency of processor reduced at least 4.4 cycles.