Research On Design And Verification Of Cache In IoT SoC

In recent years,with the popularization of the Internet and the rapid development of IoT market,applications such as smart homes have become more widespread,and people's lives have become more and more convenient.If the IoT chip with Wi Fi function is connected to the cloud,it needs to execute a large number of program instructions.Due to cost,area and other reasons,the chip cannot integrate too much SRAM,so the most commonly used program instructions are generally placed on the chip's internal SRAM.Other programs are placed in off-chip Flash.The CPU must operate the SPI bus every time an instruction in the Flash is executed,and the execution efficiency of the chip is greatly limited.Therefore,how to give a reasonable design structure and modification methods,improve the efficiency of CPU instruction fetching to a level that meets the functional requirements of the chip,and verify it with an efficient method are urgent and challenging for researchers.Aiming at the above-mentioned problem of low CPU read instruction efficiency,this paper proposes to design a read-only cache to improve the CPU read instruction efficiency.In the design process,the group associative mapping method is used to make full use of the memory space.Through reasonable division of SRAM memory and the combination of different logic functions,a variety of cache configurations can be realized.Different processing methods of tag storage information numbers are used to achieve two replacement strategies that are LRU and LFU.The division of the mapping address range,the signal conversion between the interfaces,and the constraints on the CPU's control power enable the bus interfaces AHB and EILM to read instruction data through the cache.Finally,the design index should be accepted through the FPGA test actual sending and receiving packet rate.The UVM verification methodology is used to complete the cache verification work,and a complete and highly reusable UVM verification platform is established.Comprehensive and detailed test cases are used to comprehensively verify the cache function.The reference model of the cache was constructed during the verification process,and the cache logic was re-implemented with the language advantages of UVM methods such as merged arrays,dynamic arrays,and queues;all the accessible memories in the system were managed for expected backups to ensure data correctness Make references and guarantees;accurately judge the cache hit situation by referring to the output of the model,internal signal extraction,and calculation of read instruction time.Random jumps between interfaces,coverage of boundary values,parallel and serial simulation between interfaces have comprehensively and meticulously verified the interface between the cache and the CPU,ensuring that there are no problems with interface signals in various application scenarios.Based on this,a way to configure the cache-related registers and the Flash communication path by the CPU during normal operation,and then the verify environment to take over the CPU interface for random verification is proposed.This method is more efficient and more practical.The design results show that the overall throughput without Cache is about 8-9Mbits/sec,and the throughput with Cache is about 13Mbits/sec.The verification results were reasonably evaluated.The evaluation results showed that the code coverage reached 90% and the function coverage reached 100%.The verification work was completed comprehensively.The overall results met the verification expectations.