Research On Implementation Of LDPC Decoder Based On FPGA

LDPC code has received great attention and become a research hot spot due to it's near Shannon limited performance. With the continuous research and the development of technique, LDPC code has been confirmed as channel coding scheme by several communication systems, and been applied in the DVB-S2 system. The process of LDPC decoding involves vast message, and has complicated timing sequence. So, how to implement the decoder with hardware effectively has become a research keystone.In order to implement the LDPC decoder based on FPGA, some key technologies have been studied in detail, such as decoding algorithm, data quantization, function module design and timing sequence. Firstly, this thesis has analyzed the principles and general algorithms of LDPC decoding. Secondly, this thesis has carried detailed theory analysis on BP algorithm, Log-BP algorithm, BP-Based algorithm, and Normalized BP-Based algorithm, then balanced the correcting performance and decoding complexity, for picking out the most suitable algorithm for implementation. Thirdly analyzed the major factors affecting the LDPC decoding performance, and determined the quantization scheme that met performance demanded through simulation. Module of decoding function has been designed by Verilog HDL language, according to Normalized BP-Based algorithm. And the decoder of fixed code length has been implemented on FPGA. Some verification has been executed in MATLAB and Modelsim, and the hardware testing has been completed in simulant communication system...