Design And Verification Of Baseband Data Processing IP Core For Bluetooth Low Energy

Bluetooth Low Energy(BLE)is a new type of ultra-low power wireless transmission technology.It can easily realize the interconnection between the computer and communications equipment,and also support point to point and point to multi-point voice business,data service.In recent years,BLE has already broken through the traditional Bluetooth application limitation with low complexity,low cost,low power consumption etc.,and then it has the very broad market application.So it is very important to master BLE technology.In the BLE data communication system,the development of Bluetooth hardware is the key for grasping the Bluetooth core technology,especially the development of baseband IP core.Based on Bluetooth specification 4.0 and 5.0,the Bluetooth baseband function is analyzed,and the digital baseband system architecture which operates at 2.4 GHz is designed in this paper.It highlights the design and verification of the data processing part in the link layer.Based on this architecture,first of all,Verilog HDL hardware description language is used to design sending subsystem of the baseband data processing module including framing,CRC generation,whitening and encoding,which achieves sending function of the bit stream processing.Secondly,Verilog HDL hardware description language is employed to design receiving subsystem of the baseband data processing module,which includes data synchronization processing and the receiving part of the bit stream processing.Data synchronization processing module mainly consists of four parts,sampling,correlation,symbol recovery and synchronous buffer.The receive part of the bit stream processing is mainly composed of five parts,decoding,de-whitening,frame parsing,CRC checking and the associated window.The simulation results show that when clock frequency is 24 MHz in the baseband IP core,data transmission rate can operate up to 1 Mbps or 2Mbps among code or the non-code of the physical layer.Finally,clock module of baseband IP core is designed,which includes the master-slave equipment Bluetooth clock,frame interval and enable signal.Simulation results show that the Slave will adjust its Bluetooth clock to keep synchronous with the Master after receiving the first packet successfully.Meanwhile,it achieves 150 us frame interval.After realization function of the module,BLE IP core is tested on So C architecture.The measurement results show that when the clock frequency is 24 MHz,data communication of 4.0 specification 1Mbps of non-coding,5.0 specification 1Mbps of non-coding,5.0 specification 2Mbps of non-coding and 5.0 specification 1Mbps coding can be achieved among physical layer.After ensuring that the system functions,Vivado tools are applied to integrate the baseband IP core,and to generate bit file.Then it is downloaded to the ZC706-ZYNQ development board for the FPGA verification.According to the comprehensive report,the system power consumption is 2.273 W including 2.023 W dynamic power consumption and 0.250 W static power consumption,respectively.The FPGA verification results show that bit error rate lower than 0.1% when 1740 packets are transmitted between the two Bluetooth baseband IP cores without distance.