Study On Decoding Algorithms Of Low-density Parity-check Codes For MLC Flash Memories

NAND flash memory has become an important storage medium for all kinds of portable digital devices and enterprise data centers because of its advantages of high performance,low power consumption,high storage capacity,and non-volatility.Multi-level cell(MLC)technology can be used to increase the data storage capacity of NAND flash memory by quantifying the number of charges in flash cell.Since the charge levels in an MLC cell are closer together than in an single-level cell(SLC),MLC flash memory is more prone to errors due to cell-to-cell interference,charge leakage,etc.Especially,as the size of NAND chip package scales down,MLC NAND flash memory faces severe reliability challenges.Error-correcting code technology provides an effective way to improve the reliability problem of flash memory systems with large capacity.However,classical error-correcting codes,such as RS code and BCH code,cannot meet the reliability requirements of MLC flash memory.Therefore,low-density parity-check(LDPC)codes with powerful error-correcting capability under iterative decoding have become an important error-correcting technology to improve the reliability of flash memory systems.In this dissertation,the iterative decoding algorithms of LDPC codes and their theories are thoroughly investigated for MLC flash memory.Several iterative decoding algorithms of LDPC codes for MLC flash memory system are proposed by using the characteristics of MLC flash memories,which improves the reliability of the stored data in MLC flash memories.The main research results of this dissertation are summarized as follows.1.As the bit storage density of the multi-level cell for flash memory increases,cell-to-cell interference is the dominant distortion source of flash memories.By making a thorough analysis of the error characteristics of the intra-cell bit storage channel,a bit-flipping rule for MLC flash memories is designed,and an improved bit-flipping algorithm is presented for MLC flash memories.Simulation results show that the decoding performance of the improved bit-flipping algorithm is better than that of conventional bit-flipping decoding algorithm for MLC flash memories in the same sensing precision,and the improved BF decoding algorithm for MLC flash memories can effectively reduce the average number of iterations.2.The parasitic capacitance-coupling effect may cause the distortion of the threshold voltage in a neighboring MLC cell,which leads to storage data errors of MLC flash memory.For this problem,according to the detailed analysis of the error characteristics of MLC flash memory,a bit-flipping rule of variable nodes is designed by determining the stored bit reliability by using the overlap region boundary,which is obtained from Monte Carlo simulation,of the adjacent threshold voltage distribution.Based on the bit-flipping rule,an improved bit-flipping algorithm of LDPC codes for MLC flash memories is presented.Simulation results show that,for the sensing precisions p(28)4 and p(28)5 with cell-to-cell strength factor s(28)1.8,the decoding performances of the improved bit-flipping decoding algorithm for MLC flash memories can be increased by 81% and 91% respectively,compared to the conventional bit-flipping decoding algorithm.Furthermore,the average numbers of the decoding iterations of the improved bit-flipping decoding algorithm are reduced by 9.8% and 21%,respectively.3.By using cell-to-cell interference characteristics,the two strategies of normalizing weights and adjusting log-likelihood ratio(LLR)values of iterative decoding for LDPC codes are designed under MLC flash memory channel.Based on these two strategies,we propose a weighted bit-flipping(WBF)decoding of LDPC codes for MLC flash memories to offer a better tradeoff between performance and decoding complexity.Simulation results show that,under MLC flash memory channel model,the proposed WBF decoding algorithm exhibits more excellent performances with less average number of iterations when compared with the existing WBF,MWBF and IMWBF decoding algorithms.4.The channel noises of MLC flash memory may lead to the fact that the obtained LLR values are not accurate enough,which affects the performance of soft-decision decoding for LDPC codes under MLC flash memory channel model.By determining the stored bit reliability value by using the overlap region boundary,which is obtained from entropy function of MLC threshold voltage,of the adjacent threshold voltage distribution.A dynamical updating strategy of the LLR value for the stored bit is designed.Based on this strategy,a modified min-sum(MS)decoding algorithm of LDPC codes for MLC flash memories is presented.Simulation results show that the decoding performance of the proposed MS decoding algorithm for MLC flash memories is better than that of the conventional MS decoding algorithm.Furthermore,the average number of the decoding iterations of the proposed MS decoding algorithm is reduced.5.For the problems of slow convergence and large memory consumption for MS decoding algorithm of LDPC codes with flooding scheduling,a serial scheduling strategy of MS decoding algorithm based on reliability of the stored bits is presented for MLC flash memories.Simulation results show that,for the sensing precisions p(28)5 with cell-to-cell strength factor s(28)1.9,the decoding performance of MS decoding algorithm with the proposed serial scheduling strategy can be increased by 54%,33%,36%,and the average numbers of the decoding iterations are reduce by 51%,19%,15.8%,respectively,compared to the MS decoding algorithm with flooding scheduling,layered scheduling and shuffled scheduling.