Hardware Implementation Of HEVC Key Module Based On FPGA

HEVC is the latest generation of video compression standards,mainly for high-definition and ultra-high-definition video applications.Compared with H.264,HEVC data throughput is twice under the premise of the same video quality.At present,more and more applications such as video conferencing,digital cameras,etc.require higher resolution video frames and higher frame rates,however,due to the low throughput of software solutions,it is difficult to meet real-time requirements.Therefore,HEVC hardware implementation technology research for the further development of video compression technology has a positive role in promoting.The thesis focuses on the hardware design of HEVC key module.The main contents are as follows:The thesis designs a video capture and processing system based on FPGA,deeply analyzes the structure of HEVC coding standard and the realization of HEVC video compression process,and put forward a new parallel FPGA-based hardware design architecture for the intra prediction,which effectively accelerates intra prediction speed.For the complex calculation process of intra prediction,the paper has simplified the design,and most of the multiplication is transformed into look-up table operation.The paper designs a computational unit for intra prediction,which decomposes complex operations into simple operations,and uses simple structures such as multiplexers,adders and shift registers to simplify the hardware design.Aiming at the problem that HEVC transform module has large computational complexity and high complexity,it can not meet the problem of real-time coding.In this paper,hardware optimization design of HEVC integer DCT transform is carried out,and multi-stage pipeline design of DCT transform is carried out to improve the clock frequency of circuit.In order to solve the problem of large multiplication and large consumption of hardware resources in DCT transform,the structure of the non-multiplier is designed,and the structure is further optimized to make it more suitable for FPGA implementation.Through the simulation experiment,it is feasible and effective to verify the hardware implementation of the intra prediction module and the transformation process proposed in the paper.The video compression time can be significantly reduced in the case of guaranteeing the video compression effect.