Research Of VP8 Decoding Algorithm And Hardware Implementation Of Intra Prediction

With the fast development of the information technology, video information has become an indispensable element of human life and production. The rapid development of digital video decoding technology and Very Large Scale Integrated circuit technology makes video decoding chip applied more and more widely, video decoding chip presents a broad market space and development prospects. Driven by the needs of market, research of video coding standards and corresponding hardware realizing method has become an important subject of industrial community.VP8 video is a new open source video compression format by Google company in May 2010, it’s intended to be developed into a high quality and open video format, free for everyone, VP8 has a widely potential application prospect in video conference, IPTV, the internet streaming media application field. In this context, this thesis makes a further exploration and research on VP8 decoding standard, and also analyzes the algorithm theory of the main modules.On the basis of SoC design of a video decoder, which has been successfully used in commerce, this thesis has proposed the whole realization structure and software/hardware division method of VP8 video decoder, and analyzed the theory of Intra prediction algorithm emphatically. Combined with the hardware design structure of Inra prediction module of H.264 and AVS video decoding on the chip, a hardware design scheme of Intra prediction of VP8 is given, which has been described in Verilog Hardware Language and also verified using Modelsim software. Finally, the design is synthesized on the ALTERA FPGA platform using Quartuss II software.