The Optimization Of HEVC Intra Prediction And The Implementation On FPGA

HEVC(High Efficiency Video Coding),the recently developed international video compression standard,has 50% better video compression efficiency than H.264 video compression standard at the expense of significantly increased computational complexity.HEVC allow video encoders to achieve better compression efficiencies.On the other hand,the increased complexity requires a new design methodology able to face challenges associated with ever higher spatiotemporal resolutions.Therefore,it is a very important significance thing of studying on HEVC.As in previous standards,the intra prediction in HEVC is the process of reconstructing blocs based on neighboring pixelslocated above and in the left of the current bloc.The complexity of intra prediction is especially manifested with the increasing of flexibility in coding unit structures and the number of prediction modes.This newly HEVC uses a flexible quadtree block partition structure that enables effective use of different block sizes during the prediction and transform coding process.And the test model defines 35 modes for all prediction units PU.This paper mainly studies the coding unit size decision and the mode decision for prediction unit.The main research contents of this paper include the implementation of intra prediction in HM and the implementation on FPGA.This paper studied coding units division of HEVC by sobel operator,judged the selection of predicting mode,carried out the validation experiments in HM.Compared with HEVC standard,the superiority of the proposed algorithm has been validated through testing on coding time and rate-distort performance in HM.The implementation of intra prediction on FPGA.XILINX VIRTEX6 ML605 development board is used for the implementation of intra prediction algorithm on FPGA.In practice,through ML605 board driven by Windriver,image data is transmitted into FPGA from the host computer via the DMA controller of PCIE interface under the control of the application layer program generated by WinDriver.Then intra prediction processing is carried out on the imported image data to obtain the predicted image data,which is returned to the host computer via DMA.The final processing results are observed by MATLAB.The implementation of intra prediction algorithm on FPGA includes the implementation of data storage,image division,unit prediction,reference pixel processing,mode selection,transform,quantization,inverse change,inverse quantization and other modules on VERILOG HDL.The experimental results appeal that,while image quality and compression efficiency being ensured,the coding time of optimized HEVC intra prediction algorithm has been greatly reduced in comparison with HEVC standard.Besides,the implementation of HEVC intra prediction algorithm on FPGA is applied to image compression processing.