Design And Optimization Of The Hardware HEVC Intra Encoder

ISO/IEC released the H.265/HEVC standard in 2013.HEVC intra coding gains reduction of bit rate by 22%on average over H.264/AVC while the great increasement of complexity raises the requirement for the design of the intra encoder.In this paper,through the comparison of the characteristics of the hardware and software,the necessity of the research of the HEVC hardware encoder is defined,and the design and optimization of the multiple modules of the HEVC hardware encoder are given.1?The paper studies the structure design and optimization of the mode selection module which is out of intra frame coding loop.The paper proposes one kind of traverse order,which makes the architecture produce one row(column)of prediction value of 8x8 pixel block per period under multiple modes.The scheme improves the efficiency of the model selection.With this scheme,the circuit only need 16 cycles to achieve a single 8x8 block PU traversal of the 35 models;the paper puts forward the "bottom-up and Z word scanning" partition process.It is more suitable for the design of hardware structure;the design of the reference pixel selection scheme with low resource consumption is designed.The circuit can obtain the reference pixels from the fixed memory address with the scheme,which greatly reduces the consumption of the selector,and significantly saves the circuit area;the paper designs a special mode traversal circuit of 4x4 small size PU block,the experiment shows that the design of the branch can greatly improve the throughput of the module;furthermore,detailed design and optimization of the functional circuit in the module is proposed.Compared with the prior architecture,this model has the advantages of high work efficiency and effective control of the circuit area.2?The paper designs several modules in the HEVC intra frame coding loop later:(1)On intra prediction module,the paper designs a flexible storage circuit,which decide whether to store or where to store according to the space position and emergency degree of invoked of the reconstructed pixels.Thus,the storage area is reduced,and the acquisition of reference pixels becomes more convenient.(2)In the design of the HEVC integer DCT transform module,this paper studies the butterfly fast algorithm,and designs a reusable butterfly operation circuit based on the characteristics of the algorithm.At the same time,this paper designs multiple constant multiplication circuit,which uses shift add circuit instead of multiplier.Then,this paper also proposes the further reuse of the overall structure.The experiment results show that the structure has a high parallel and consumes less circuit area,(3)In the HEVC quantization module,this paper designs the overall structure of the quantization module,and puts forward the hardware optimization scheme,which uses the look-up table instead of the modular calculation and division operations.