VLSI Design And Implementation Of Depth MAP Intra Prediction In 3D-HEVC

With the development of 3D video technology,the high efficiency video coding standard has launched its 3D extensions,which is named 3D-HEVC.The 3D-HEVC standard encodes video using the multi-view plus depth format,which adds depth maps as auxiliary encoding information.Since the characteristics of depth map and texture map are not same,the 3D-HEVC standard adds the depth modeling modes as one of the intra-prediction modes for depth map.The DMM algorithm can better encode the depth map,but it has higher complexity and takes longer coding time.To solve this problem,this thesis proposes two new hardware architectures and designs the DMM-1 hardware accelerator.The main work of this thesis includes the following aspects:(1)The hardware circuits of DMM-1 algorithm with multiple parallel architectures are implemented.In this thesis,the DMM-1 algorithm is studied.According to the non-correlation characteristics of the data,the circuits of DMM-1 algorithm with fully-parallel,2-partial parallel and 6-partial parallel architectures are designed and implemented.The hardware circuit of the parallel architecture achieves a significant reduction in coding time by simultaneously calculating the wedgelets through several same calculation units.Compared with the experimental results: the coding time of fully parallel architecture is reduced by 92.34% on average,the 2-partial parallel architecture is reduced by 68.84% on average,and the 6-partial parallel architecture is reduced by 34.03% on average.(2)The hardware circuits of DMM-1 algorithm with pipeline architectures are implemented.The multiple parallel architectures hardware circuits increase the resource consumption while reducing the coding time.In order to solve this problem,this thesis designs a pipeline architecture circuits of DMM-1 algorithm.Combining the advantages of partial parallel and pipeline architectures,the hardware of DMM-1 algorithm with partial parallel pipeline architecture is designed.By splitting the calculation process of the DMM-1 algorithm into five sub-modules,each sub-module constitutes one level of the pipeline architecture,achieving a reduction in coding time without increasing hardware resource consumption.Compared with the experimental results: the coding time of pipeline architecture is reduced by 30.50% on average,the 6-sets partial parallel pipeline architecture is reduced by 84.90% on average,and the 2-sets partial parallel pipeline architecture is reduced by 65.16% on average.