| As digital video technique becomes more and more widely used, the trend that analog video signal will be substituted by digital video signal is inevitable. In this interim, the video processing IC has quite a practical value and market prospect. Its main purpose is to transfer video input signals of different forms to video output signals of specific standard forms by the way of DSP. Its main functions are de-interlacing, frame rate up-conversion, scaling, quality improvement and etc. How to process and move the enormous data is one of the main problems we deal with.This thesis focuses on design and realization of the data cache system in our video processing IC. Due to the importance of the data control and write-and-read mechanism, much introduction and analysis will be put on those parts. At the same time, the real-time performance of the data cache system will also be discussed. With some critical advantages, such as small area, low cost, high speed and large volume, SDRAM becomes the ideal external memory for the video processing IC. As the basic unit, SDRAM has the responsibility of storing all the data in the video processing procedure. Therefore, the designing and debugging of the SDRAM controller is quite an important job. After carefully studying the operation of SDRAM, in this article, I focus on the design and PCB level debugging of the SDRAM controller, which include HDL coding, write-and-read timing analysis and testing. The SDRAM controller I made, which has an adaptable ability and can easily be extended to various systems, adopts handshake signals and can be directly used as an IP core.A top-down design procedure was used in the design process. Design regulation, module dividing, function simulation and synthesis are also discussed in the article. The whole device has been tested and used in the video processing system. The result perfectly met the design demand. In FPGA test, SDRAM controller is working at the frequency of 100MHz. |
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