| Video Signal Processing Chip is one of digital TV core chips. This chip's main function is to converse the digital signal source to the format of the target display. In addition, it has some other function utilizing the adjusting of OSD menus. The research background of this thesis is Tianjin municipal science and technology development program - Video Signal Processing IC research. Video image scaling is an important composing part of this chip.The thesis brings forwards an adapted video processing algorithm and hardware implementing achitecture through researching and analyzing the current video image scaling algorithms, and finally presents the result of test and FPGA validate. This papers researches two of current main algorithms: based on pixels'positions interpolation and based on image content interpolation. It adopts cubic spline interpolation and two interpolation algorithms based on edge detect (direction correlation interpolation scaling and Lapalace edge detect interpolation scaling). It implements a comparatively simple scaling module circuit architecture adoping cubic spline interpolation, on this condition, the edge detect algorithm detects the edge of image and uses rhombic linear interpolation along the edge to eliminate the lost of image information along the edge. By contrast with cubic spline algorithm, the interpolated result image of the algorithm based on edge detect has the better quality. And it implements a configurable and expansible format conversion function through adapting OSD menus by external MCU controller.In the mean time, we uses top-down design method, and follows the popular way of IC designing including: dividing system into function modules, designing RTL coding of each modules, software function simulating, logic synthesizing and FPGA hardware function validating, and finally designs a configurable IP core. Until now, this chip has completed the FPGA validate, and has been checked and accepted by Tianjin science and technology committee. |
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