Design And FPGA Implementation Of Uplink And Downlink Physical Layer Receiver In LTE-A System

Owning to the characteristics of time-varying and uncertainty of the channel environment in Long Term Evolution Advanced(LTE-A), receiver needs to process the received signal in order to recover the sent signal at the greatest extent. During this procedure, the design of physical receiver at the receiving end has become particularly important for ensuring the correctness of the received data. Based on the project demand of National Science and Technology major project ?experiment equipment development of TD-LTE-Advanced system?, on the foundation of baseband platform used in the project, physical layer receiver has been designed and implemented using Field Programmable Gate Array(FPGA) in this thesis, which supports single antenna receiving in uplink and two antenna receiving in downlink.In the beginning of this thesis, the research background and significance of the physical layer receiver are introduced and current research status in both domestic and oversea are studied. Then the characteristic of the system and key technologies of LTE-A are summarized. With the introduction of process of uplink share channel and downlink share channel and baseband development platform, the overall structure and design partitioning are presented. Besides the design and specific description of Radio Frequency(RF) module and synchronous External Memory Interface A(EMIFA) interface module, which involves less algorithm are studied. By means of analysis of the generation of baseband signal at the sending side, decoding baseband signal designing is presented and the generation process of reference signal, basis of channel estimation is studied. During the study of channel estimation, this thesis not only analyzes the channel estimation algorithm used in the location carrying reference signal such as Least Square(LS) and Linear Minimum Mean Square Error(LMMSE) algorithm, but also studies several interpolation algorithms used in the location of data, using simulation with MATLAB software to compare and contrast the performance of algorithms. Then signal detection algorithms such as Zero Forcing(ZF), Minimum Mean Square Error(MMSE) and decoding Space Frequency Block Code(SFBC) are studied and compared in terms of performance. As for the inefficiency of using mutual information between channel estimation and signal detection, this thesis presents joint channel estimation and signal detection algorithm. The simulation result shows that its performance is better than traditional algorithm which estimates channel firstly and then detects signal. Balancing between algorithm performance and computation complexity, combining with requirement of the project, schemes of channel estimation and signal detection are designed with the selected proper algorithms.According to the design of each module, implementing the receiver design with FPGA using Verilog Hardware Description Language, analyzing the implementation in detail, and testifying each module with Modelsim simulation, the thesis analyzes the performance of the receiver in terms of resource utilization and time consumption, which shows the design of receiver can meet the requirement of the project. In the end, by making joint debugging with Digital Signal Processor(DSP), the validity of implementation is verified in the thesis. The design has been applied in the project, which has a certain reference value to other receiver design of different communication system.