The Design And Implementation Of Receiver Of GPS/BDⅡ Based On FPGA And ARM

Location and navigation is one of the largest and most popular technology of information industry, and USA has established the Global Positioning system(GPS) based on satellite years ago. The technology and market of GPS have become fully mature, and GPS has held dominant position in the field of satellite navigation. Many regions and countries such as the EU, Russia and China unceasingly endeavor to develop their own navigation and positioning system and improve the industrial chain. The domestic-made navigation system which is of R&D-by-self is BeiDou navigation satellite system(BDS). Beidou 2nd Generation Satellite Navigation System(BDII) is still at the early stage of realizing basic position, consequently, is the researching hotpots currently. At present, there are very few receiver chips of BDII in the market, in addition, the technology is not well developed and they perform poorly. Therefore, designing a hardware receiver of GPS/BDII is of great importance.This paper introduces the design and implementation of GPS/BDII civil signal hardware receiver based on FPGA and ARM. Firstly, it presents the related background, theory of knowledge and the required processing process of GPS/BDII receiver. Secondly, it gives the design of hardware circuit of GPS/BDII receiver, including the design of the circuit of antenna and RF circuit, and the relevant circuit of FPGA and ARM. Then it describes in detail the principle of the function realized by FPGA, as well as the simulation and realization of the algorithm. Finally, the principle of the function realized on ARM together with the simulation and realization of the algorithm are proposed. The main line of this article is the data processing flow. On the basis of it, this paper introduces the data processing steps such as RF signal amplification, filtering, down conversion, analog to digital conversion, acquisition, tracking, bit synchronization, frame synchronization and positioning solution and realization. The acquisition and tracking steps are the researching hotspots in satellite navigation. Consequently, by simulation with MATLAB and Verilog, in this paper, we propose an improved algorithm of how to search code phase parallel using FFT, and give out the result of modelsim and implementation in FPGA. Specifically, the two order frequency lock loop aided three order phase locked loop to track carrier phase is used in in tracking stage. And the specific implementation details and optimization of realizing the algorithms in FPGA are given in this paper. Besides that, the ARM processor is mainly responsible for the process control, data analysis and positioning solution and process. At the end of the paper, we investigate and verify the correctness of hardware and software modules of the receiver, analyze the results of the tests, make comparison with the dual-mode location module on the market, and put forward some ideas and breakthrough that can be applied in the future.