Research On Key Technology Of Data Receiving Based On MAC Of PCIE4.0 Physical Layer

With the explosive growth of information technology,the bandwidth and speed of the bus have gradually become the critical factors that restricted the development of computer systems.The PCIE(Peripheral Component Interconnect Express),which serves as the third generation high-speed I/O serial bus,has overcame the interference and synchronization issues of parallel buses.Its high-rate data transmission makes it have a wide development prospect in the fields of computer and communications.The physical layer is the bottom layer of PCIE.MAC(Media Access Control)is the logical part of the physical layer,which is connected to the data link layer and the PCS(physical coding sublayer).Thus,the MAC plays an important role in PCIE system architecture.This thesis focuses on the key technology of data reception in MAC,designs and verifies of related modules.The specific research contents are as follows: 1)Analyze the PCIE protocol and physical layer MAC related technologies,including the division of physical layer,data package structure in PCIE,LTSSM(Link Training and Status State Machine),ordered set and multi-lane data stripping rules.2)Further research on the key technologies of receiver,including lane-to-lane De-skew,descrambling and link equalization.To solve the problem that the traditional De-skew logic cannot meet the high-rate requirements,this thesis proposes a De-skew logic scheme based on synchronous FIFO and adopts two schemes in the design to meet the different rate requirements.In addition,this thesis uses the parallel descrambling method to avoid the disadvantages of traditional serial descrambling that are low in efficiency and difficult to achieve high rates.3)Based on the further study of PCIE protocol,the thesis elaborates the framework of MAC,and the design and implementation of each receiver's sub module.Block diagrams,flow diagrams,state transition diagrams,and module key signal lists are used in this thesis to describe in detail the implementation methods of each functional module.In the specific engineering practice,Verilog language is used to achieve RTL design,and System Verilog language and VIP core are used to build platform for verification.Then use Synopsys' s VCS and Novas' s Verdi to run the functional verification.The verification results illustrate the design has meets the expected function.After completing the functional verification,logic synthesis and timing verification are implemented by Design Compile for RTL code.The results illustrate the design can work normally at the clock frequency of 250 MHz.Finally,Xilinx's Vivado tool is used for FPGA verification to further insure the validity of the design.The PCIE4.0 physical layer MAC receiver designed in this thesis can meet the rate requirement of PCIE4.0 when the working frequency is 250 MHz.It achieves multi-lane high-rate data reception,improves the link transmission efficiency,and has some practical value for high-rate data transmission.