| Low Density Parity Check Code(LDPC)is a code whose performance can reach the shannon limit,and has been applied in many fields since the 21st century.In order to standardize the application of LDPC codes in the field of deep space communication,the Advisory Committee on Space Data Systems(CCSDS)has formulated a set of standards for the application of LDPC codes in deep space communication.Deep space exploration in space activities is inseparable from reliable deep space communication technology as a basic guarantee,and related research on deep space communication technology is constantly gaining more and more attention.After Gallagher created the LDPC code,it was ignored by people for more than 30 years due to the technological conditions at that time.Until the rise of Turbo codes in the 1990s,scholars from various countries began to study LDPC codes again.After the LDPC code is re-emphasized,its structural design,hardware implementation of encoding and decoding,and application in the field of digital communication have quickly become the focus of research.The LDPC code recommended by CCSDS is a code with high error correction gain performance,which can significantly improve the transmission gain of the channel in deep space communication,and is very suitable for deep space communication.Therefore,it is a great significance to designing an efficient LDPC codec topromote the deep space applications improving.The main research work of this thesis are as follows:Firstly,according to the characteristics of quasi-cyclic LDPC codes,an encoder based on cyclic shift register structure is designed using Verilog HDL language,and its modules are analyzed and studied.Then the logic synthesis of the designed LDPC encoder is carried out.Based on the SMIC 65 nm radiation-hardened standard CMOS process library,the constraining circuit clock clk frequency is 97.1 MHz.First convert it into a netlist,perform back-end synthesis,and get the encoder’s timing,area and power consumption report.The results show that the area of the encoder,total power consumption,maximum operating frequency,and throughput after intergrtionare 227934.51μm~2,10.6246 mW,and 97.1 MHz,respectively.At 776.8 Mb/s,the final result meets the design requirements.Then use the simulation software is employed to simulate the encoding algorithm and compare it with the encoder results,which proves the correctness of the encoding results.Secondly,the simulations were carried out for LDPC codes,convolutional codes,BCH codes and Hamming codes of the CCSDS standard respectively,and the advantages and disadvantages of various decoding methods were compared and analyzed,by the decoding method of LDPC codes which suitable for deep space communication conditions was selected.The hardware design of the partially parallel BP decoder is completed based on Verilog language.Then,the designed LDPC decoder is also logically integrated,and the timing,area and power consumption report of the LDPC decoder are obtained.The integrated area of the decoder is 3742945.84μm~2,the total power consumption is 7.9053mW,the maximum operating frequency is 97.1 MHz,and the throughput is 776.8 Mb/s.The research results indicate that the design can meet the decoding function and performance requirements.Finally,use the Encounter software of Cadence Company is used to complete the layout design of the LDPC decoder circuit,and the result shows that the generated layout area is 1.9×1.9μm~2.Totally,the above research results show that the designed and generated encoder has low coding structure complexity and well decoder performance,which can meet the application performance requirements in the environment of deep space communication. |
