Research On Successive Cancellation List Decoding Algorithm Of Polar Codes And Fpgaimplementation

In modem society, with the rapid development of digital communication technology, the reliability requirement of digital communication system is correspondingly increasing. and the demand for higher data-rate transmission is correspondingly growing. Channel coding is one of the effective methods to improve the reliability of communication system, so many scientists have searching the coding imethod which can achieve Shannon capacity for decades. Polar codes,recently introduced by Arican, are a significant breakthrough in coding theory. It is proved that polar codes can achieve the channel capacity. Polar codes will be widely used in future digital communication system because of it's low coding complexity. This paper focuses on the successive cancellation list (SCL) decoding algorithm and it's hardware implementation of polar codes. The main work are as follows:(1) Improving the decoding algorithm of polar codes. Successive cancellation (SC)decoding algorithm is analyzed. The SCL decoding algorithm and a variety of enhanced SCL decoding algorithm are explored in deep, such as cyclic redundancy check (CRC) aided SCL(CA-SCL) algorithm, adaptive CA-SCL (aCA-SCL) algorithm and partitioned CA-SCL(PCA-SCL) algorithm. Then we design the leaping algorithm which can reduce the decoding delay obviously. And the adaptive PC A-SCL (aPCA-SCL) algorithm is designed, simulation results demonstrate that the mean of search size can reduce 11% - 42% when SNR ? 2.0.(2) Hardware implementation of aPCA-SCL decoding algorithm. Firstly, improve the algorithm to adapt hardware implementation. Secondly, a quantization scheme with less resource usage and less performance loss is proposed, we quantize the channel loglikelihood ratio (LLR) with 4 bits, the other LLR with 6 bits, and the path metric with 8 bits. Compared with the floating point performance, the performance loss less than 0.1 dB. Finally, the hardware design of each module is introduced in detail, the folding partial-sum network is improved to adapt to the leaping decoding algorithm and the "Lazy Copy" technology is adopt to reduce the waste of path copy. Moreover, the speed of the optimized sorting network has increased 35.43%.(3) Completing the RTL function simulation of the aPCA-SCL decoder. Then building a complete system with test link and PC to accomplish FPGA verification and performance evaluation.Simulation results demonstrate that for polar codes N = 1024, R = 1/2, P = 2 ,Lmax-4, using DE5-Net board, the maximum frequency is 212.27 MHz, the maximum throughput can achieve 114.22 Mbps. Compared to the PCA-SCL decoder, the throughput increase more than 24.60% when FER ? 0.01.