Research On Polar Codes Decoder And FPGA-Based Implementation

Polar codes were first proposed by Ar(?)kan as a theoretically proven coding scheme that can reach the channel capacity.Despite having only a decade of development,polar codes has got outstanding achievement due to its superior performance.It was chosen as the 5G-eMBB channel control coding solution in 2016.When the length of polar codes is short,and the performance of polar codes is poor because the polarization is not obvious at that time.The decoding time delay will increase as the length of polar codes increases.In the future,communication will require lower latency and higher throughput.In practical applications,polar codes still have a lot of room for development.And this thesis will look into how to design a polar codes decoder on hardware with low latency and high throughput.The SC decoding algorithm is described in Arikan's paper on polar codes,although it is for bit-by-bit decoding,and the decoding time is relatively considerable.In this thesis,we will look at the fast SC decoding algorithm,which does away with single-bit decoding.By breaking polar codes into sub-codes,the fast SC decoding technique can decode a collection of codewords at once,considerably reducing the decoding time delay.In this thesis,we focus on both hardware and software aspects of the fast SC algorithm.The program primarily simulates the algorithm's performance and provides software implementation of the algorithm's sub-code division module.In terms of hardware implementation,FPGA is used to complete the design of fast SC decoder:1.The splitting of polar codes into four distinct sub-codes is at the heart of the quick SC decoding process,and the division method is not unique.Every sub-code is decoded using the fast decoding algorithm.The length of the divided sub-codes is found to have an effect on the decoding delay in this thesis,and the length is longer,the decoding delay is shorter.As a result,in this work,we offer a recursive partitioning algorithm that ensures the optimum partitioning of sub-codes.By simulation,this thesis demonstrates that the fast SC decoding technique has no performance loss when compared to the regular SC algorithm.Simulates the decoding performance of the fast SC decoding algorithm under different code lengths and code rates using the control variable approach,and the results are essentially the same as the SC algorithm.2.This thesis examines the use of storage units and calculation units in FFT,tree,and linear decoder structures,and concludes that the tree structure is relatively simple in construction and consumes fewer resources than the other two.Because the tree structure is better,use it to create the decoder in this thesis.Fixed-point quantization is essential for floating-point numbers since the hardware cannot handle them.This paper uses simulation to prove that16-bit quantization of the received signal's log-likelihood ratio has almost no performance loss.3.The control module,log-likelihood ratio calculation module,partial and feedback module and fast decoding module are the major components of the decoder.In log-likelihood ratio calculation module,Function f and function g are integrated into one processing unit in the implementation of the log-likelihood ratio calculation module to save hardware resources.Hardware resources are optimized for each specific sub-polar code in the fast decoding module.Finally,a fast SC decoder with a code length of 128 is designed using Xilinx's7z020clg400-1 development board.Comprehensive simulation results show that the hardware resource consumption of the decoder is less than 3%,and the throughput rate is43.54 Mbps when the clock frequency is 50 MHz.