Research On Decoding Algorithm Of Polar Codes And Implementation

With the development of digital communication technology, human’s requirement of high reliability of digital communication system is correspondingly increasing. Channel coding is an efficient method to enhance the performance of communication system, so capacity achieving codes have always been the research hotspot in coding theory. Polar code, recently introduced by E.Arikan, is a major breakthrough in coding theory. It is the first proved capacity achieving code over the binary-input discrete memoryless channel (BDMC), which also have regular code construction. Because of its regular coding structure and low coding complexity, it has emerged as the most favorable error correction code in coding theory.Two main decoding algorithms of polar codes are successive cancellation (SC) decoding and belief propagation (BP) decoding. However, the large code length required by practical applications leads to high decoding latency because the conventional successive cancellation (SC) decoder decodes bits serially. This paper first reviews the conventional SC decoder briefly. An improved SC decoder architecture is given, which reduces the decoding latency by 25% compared to the conventional one. Then a stage-reduced SC (SRSC) decoding algorithm and its low-latency architecture is presented. Compared with the conventional SC decoder, the proposed stage-reduced SC decoder achieves almost 50% latency reduction with no performance degradation.BP decoding performs better comparatively and more importantly, it is inherently parallelizable. Due to the large number of stages and short critical path of the conventional BP decoder, a memory efficient stage-combined belief propagation (SCBP) decoder design for polar codes is presented. Firstly, we briefly reviewed the conventional BP decoding algorithm. Then a stage-combined BP decoding algorithm which combines two adjacent stages into one stage and the corresponding belief message updating rules are introduced. Simulation results show the proposed algorithms can half the number of stages without performance degradation. Based on this stage-combined decoding algorithm, a memory-efficient polar BP decoder is designed. Synthesis results show the proposed decoder achieves 50% memory reduction, significantly cuts the decoder area, reduces the decoding latency, and increases the throughput.