Hardware Architecture Design And Simulation Verification Of Polar Coding And Decoding Algorithm

The Polar code is an error-correcting code constructed based on the phenomenon of channel polarization.It is currently the only method that can be strictly proved to reach the fragrance limit.In addition,Polar code has a very simple encoding method.Initially,Arikan adopted The serial-cancellation(SC)decoding algorithm that best complies with the recursive structure of Polar code encoding decodes it.The same SC decoding algorithm also has strong recursiveness,which is very suitable for hardware implementation.On November 17,2016,the Polar code was officially confirmed as a coding scheme for the control channel of the 5G eMBB scene,which made the excellent characteristics of the Polar code truly reflected,so the research on the Polar code is also of great practical significance.In this thesis,the principle of Polar code encoding and decoding is explained in detail,several decoding algorithms are given,and an SSCS decoding algorithm is proposed.The encoder implementation of the Pola code and the FPGA implementation design of the SSCS decoder are given.Finally,simulation verification was performed.The work done and results obtained in this thesis are:1)Starting from the phenomenon of channel polarization,the specific implementation process of the two stages of channel association and channel split in the channel polarization principle is introduced,and then the principle of channel polarization is explained from the perspective of information theory.According to the obtained Matlab simulation results,It is more intuitive to observe the existence of polarized channels.Then,the reliability estimation methods of several polarized channels are introduced in detail.Finally,the encoding method of Polar code is given.2)Based on the SC decoding algorithm,and based on its poor decoding performance at short code lengths,the SCL and CA-SCL decoding algorithms with excellent decoding performance are introduced.The decoding algorithm is simulated to verify the improvement of decoding performance.Based on the consideration of high delay of serial decoding of SC algorithm,a simplified SC(Simplified SuccessiveCancellation,SSC)decoding algorithm is introduced.The SSC decoding algorithm simplifies the SC without sacrificing decoding performance.The calculation reduces the delay time of SC decoding.In addition,considering the high complexity of multiple decoding paths of the SCL decoding algorithm,a Continuous-Cancellation Stack(SCS)decoding algorithm is also introduced.The decoding performance of SC and SSC algorithms,SCL and SCS algorithms are compared and analyzed by Matlab simulation.Finally,an SSCS decoding algorithm is proposed,and the decoding performance is also verified by Matlab simulation.3)The design of Polar code encoder and SSCS decoder is realized based on FPGA.The corresponding FPGA implementation architecture is given according to the encoding principle of the Polar code and the decoding principle of the SSCS algorithm,and the workflow of the hardware architecture is explained.The overall hardware architecture of the coder adopts a modular design concept,including Many sub-modules based on implementation functions.This article also designed the hardware implementation methods of each module.Finally,based on Verilog language,some of the core modules were simulated on the joint platform of Vivado and Modelsim to verify the correctness of their functions.