Research On Algorithms Of Encodingand Decoding For Polar Codes And Implementation Of The Decoding Algorithm On FPGA

The channel capacity theorem is proposed innovatively by Shannon in 1948, marking official establishment of channel coding theory, whose technological co re is to improve transmission reliability of communication systems by increasing the redundancy. Although with years of development, there had not been any encoding and decoding schemes which could reach the Shannon capacity. Until the Arikan proposed polar codes, the history had been changed. Once proposed, polar codes attracted widespread attention from the academics due to its capacity achievement. At the same time, because the polarization is a common phenomenon in many communication scenarios, polar codes will have very broad developmental prospects in future communication systems.Firstly, we analyze and study the coding theory and algorithms of polar codes in this dissertation. The basic principle of the channel polarization is expounded theoretically, and the general combining and splitting process of polarization channel is discussed in detail. Based on that, this dissertation expounds the polarization coding theory and analyzes the specific encoding process of polar codes. Since polar codes are constructed based on the polarization channel, the reliability estimation of the polarization channel is mainly studied. We compare the advantages and disadvantages of two common channel estimation methods, and analyze the performance of two kinds of channel selection methods which are Bhattacharyya parameter and Gaussian approximation(GA). Experimental results show that the GA of the polarization channel constructing method is more practical to improve the decoding performance of polar codes.Secondly, this dissertation analyzes and studies the decoding algorithms of polar codes. The code tree of polar codes is expounded theoretically and the theory of successive cancellation(SC) decoding is discussed in detail. With the fact that the performance of the SC decoding algorithm under the situation of finite codes length is not ideal, we study the successive cancellation list(SCL) decoding algorithm further and propose the non-recursive SCL decoding algorithm, which greatly enhances the efficiency of decoding. Furthermore, this dissertation discusses the performance improvement of SCL decoding algorithm affected by pruning algorithm and the cyclic redundancy check(CRC). In the consideration of the hardware implementation of the decoding algorithm, the quantizatio n scheme of SCL decoding is studied, and the uniform quantization method based on the log likelihood ratio is adopted.Finally, the hardware implementation architecture of the decoding algorithm is proposed. In this dissertation, the FPGA implementation of SCL decoding algorithm of polar codes is discussed in detail, and the design idea of the internal composition module is introduced systematically. Besides, in order to realize the simulation test of the hardware platform, the Matlab and FPGA joint real-time debugging method based on serial communication is designed, which is simple and convenient. By using the test platform, the correctness of the hardware architecture o f the decoding algorithm of polar codes is verified, and the simulation results are in agreement with the theoretical algorithm. Besides, the decoding performance and resource usage of the polar codes decoder are analyzed.