The Design Of A Synchronous Step-down DC/DC Power Management Integrated Circuit With I~2C-Compatible Interface

With the rapid development of domestic integrated circuit and the dramatic increase in consumer electronics such as mobile terminal,the industry proposes all-round challenges for design and optimization of the power management integrated circuit(simply,PMIC),this is because the PMIC with high performance,strong flexibility is feeding strong market demand.This paper explains the design of a synchronous step-down DC/DC PMIC with I~2C-compatible interface based on the application trend of intelligence and digitization.The PMIC in this paper is designed and implemented from the following three aspects:1.In order to reduce intrinsic loss of the PMIC and fully improve efficiency,among all the module,the chip mainly focuses on the design of the zero detection circuit and power transistor to reduce significant influence of the conduction losses on efficiency in light load and heavy load respectively.In addition,quiescent current of bandgap inside the chip needs to be minimized as much as possible for reducing quiescent losses.Eventually,the efficiency of the chip in a full-load range achieves up to 84.9%~90.8%.2.For different load values against microprocessor in the standby mode,low-speed data processing and high-speed data processing mode,the PMIC needs to be able to respond quickly to this change of load when these working modes are switched.However,the traditional voltage-mode and current-mode controls are limited by bandwidth of the error amplifier and its compensation circuits.Therefore,this paper uses the advantages of constant on-time control in response,improving the transient response effectively.3.For the problem of the traditional PMIC cannot adjust the output voltage accordingly based on the different working state of the system so as to save the power consumption of the entire system,this paper chooses and integrates I~2C interface to realize the minimum adjustment of 12.5mV steps after analyzing the advantages and disadvantages of various serial interfaces.That is to say,this approach improves flexibility of the PMIC in the application environment.This paper adopts the cost-efficient CSMC 5V 0.5um 2P2M CMOS process which has advantages of less number of mask and fewer number of lithography and completes the tasks like circuit design,simulation as well as layout with Cadence and VCS platform based on mixed-signal simulation,and board tests after taped out successfully.It is found that the chip designed in this paper can meet the requirements of design index,and achieve the function of the synchronous step-down DC/DC PMIC with I~2C-compatible interface.